Hello,
I need to brake-out from a 0.4mm BGA.
The reference design from the manufacturer uses filled microvias just below the BGA pad to reach the next level of copper.
KiCad won’t allow me to place a blind/buried via or a microvia right below the pad: ErrorType(4,7): via near pad
Disabling the DRC enforcement would allow me to place the via where I want but of course any DRC check does flag the via afterwards.
Is there a way to setup KiCad to allow vias under BGA pad?
Thanks
Are you sure the error is generated by the pad with which the microvia is connected?
Can it be that the clearance settings mean that one of the neighboring pads is too close? (In kicad there is no drc error generated if two parts of the same net get too near to each other.)
Can you make a screenshot of the surroundings of the pad and give us the exact drc error message. (we would need the net information given there.)
Rene, you a right!
The interfering pad was not the one belonging to the track but the one next to it.
Here is a screen for future reference.
Thanks David for the useful info!
Thanks!
Your screen shot seems to have some wide tracks directly connecting to the pads. The App notes emphasize balancing the thermal load on each pad to get good quality soldering.
I have never done a 0.4mm design, something I want to avoid for now
That is a very good point David.
I was somewhat concerned about it too when I started to follow the reference layout from the datasheet (MAX77818).
But in this picture none of the pads have thermal relief!
However, MAX actually has an eval board for this component and they provide layout layers with it! The layout in the eval board is quite different, looks more balanced!
Thermal reliefs would matter if the component tries to sink heat into the pads while operating, and you wanted to balance the heat-sink capacity of each ball.
Otherwise, thermal reliefs are only there to help with spot soldering (hand soldering,) and reflow soldering doesn’t need it at all. A wider connection to the pad is otherwise generally better because it has lower resistance.
(Edit: as pointed out below, for tight pitch BGA, there are additional problems to consider)
Section 13 of the TI document says “The challenge with fine pitch board design is to insure that traces and vias don’t pull heat away from the solder ball pad”
I keep thinking of reflow soldering as a homogenous temperature process (“bake at 240C until done”) but of course it isn’t. Thanks for pointing out that the fairly brief peak in a typical reflow profile doesn’t heat the board and components evenly – there’s only 8 - 10 seconds of the peak temperature, so I guess this does actually matter!
Guys
I’m also looking for a way to do via in pad.
For a part which is basically a BGA, just with only 2 rows of pins around the outside
So far the best I’ve been able to do is to duplicate the pads and put them on both the top F.Cu and the bottom layers
Ideally I need the symbol to know it can be routed to on the top and inner 1, or I guess all copper layers
Unfortunately the footprint editor doesn’t allow SMD pads to have “all copper layers” selected
And I still havent figured out if its possible to enable 4 layers in the footprint editor
Is there a work around for this e.g. somehow edit the file and change the layer number ?
Edit.
I seem to have partially made this work by duplicating opening the mod file and duplicating the pins but in the duplicate I changed the layer name from F.Cu to In1.Cu
But, Goodness knows what the gerber etc file output would contain, I guess it will be missing the commands that insert a via into these pads.
@rogerclark Did you manage to create a perfect footprint for the nRF52840? Would you mind to share it?
I tried to create a footprint for this device but found it was impossible to produce in KiCad.
Although its possible to create a footprint with pads on the top layer, its not usable because I could not route tracks from the pads, as the spacing between pads is too small.
The nRF52840 has specific requirements for tracks e.g. to the antenna and power and ground, and you can only do this with via-in-pad
Unless something has changed recently, KiCad does not have Via-in-pad, and therefore you can’t make a create a usable footprint.
I tried try experimenting with placing the SM pads on the middle layers to approximate what you get with Via-in-pad, but as far as I can tell, this didn’t result in the layers being joined together by a via etc
You may be able to hack the resultant gerber files manually to add whatever commands are needed to create vias in the appropriate locations / pads, but the process would be difficult and prone to errors.
Also, ideally the process of assigning vias, needs to be done by PCBNew and not as part of the footprint, because its only when you lay out the PCB do you know which pads on the device need to be via’ed and to which layers.
Currently, you’d constantly need to keep changing the footprint, as you tried to route your design
In the end I gave up on using this device, so as the project was speculative, I decided not to proceed.
Hi All,
Is there a way to do pad in via in V5.1.0?
I have a 25 pin 0.4 mm BGA (WLCSP25) and it is quite tight I would like to do pad in via if possible.
Otherwise do you have any suggestion? how could I route this?
Cheers!
How does kicad stand in the way of doing this? I thought the main topic would be your manufacturing chain as one needs filled vias for via in pad. (The only thing i could think of where kicad might be limited is that there is no obvious way to set specific vias to be filled. But i am not sure if there is even a way to include this in a gerber file so i would guess this would be something that you need to communicate in some other way anyways. For example by using a special drill diameter for vias that need to be filled or by adding notes on a technical layer.)
A via is a small hole. and a pad usually is a bigger piece of copper.
The pad won’t fit in the via, and even if it fits there is nothing for the pad to adhere to.
You probably meant via in pad.
Unless you eat a car before you drive to work.
As Rene said there is no limitiation in KiCad to prevent this and it can be designed in KiCad. The limitations and potential problems are with manufacturing the PCB and automated assembly / soldering. The most obvious problem is with reflow soldering and all the solder gets sucked into the via hole and there is not enough left to form a reliable connection. For this reason the via’s are often filled, which is an extra step during procuction, and not all PCB manufacturers can do this.
The thread is about 0.4mm BGAs, so we are talking about a 4/4 level PCB maker. There is no way that this sort of board is going to be made by anything but an (expensive) specialist.
Identifying the filling is going to be a an extra detail drawing, there is no option in the older Gerber standards for this.
This thread has been hijacked twice.
First 2 years ago by RogerClark, with a BGA with 2 rows of balls that would not need filled via’s at all because there is plenty of room for via’s in the center area.
And recently by leardilap, who has an unknown experience and might well be a beginner with no clue about the tradoffs of using a WLCSP25.
https://www.nxp.com/docs/en/package-information/wlcsp25_217x232_po.pdf
I agree, fine and complex BGA design is hard.
I have only done the coarser end of the BGA package range and had yield problems with that.
