Zone violates minimum width and thermal relief settings

[kbless7]

I have a project that I made in v6; I just installed v7.0.7, so I am converting it to v7 but am running into PCB Editor issues with a filled zone. The front layer ground zone ignores the minimum width and thermal relief settings. There is no issue with any other filled zone or ground planes in the other three layers.

The first image below shows the zone settings and part of the PCB with:
• Pads not having thermal reliefs
• Copper sections smaller than minimum width
• Copper slivers and points despite setting 0.25mm fillet radius

This was not a problem in v6, so I don’t know what has happened in v7 to cause this. There are a few oddities I have found.

1. If I set the minimum width to 0.29mm or larger, then it behaves properly. Not a solution since I need 0.25mm to match everything else.
2. If I increase the zone priority to 3 or higher it works properly. Not a solution since it’s the ground plane and would overrule more critical zones.
3. If I put a keepout zone in a specific area then it works!? See the second image. There isn’t anything around the keepout zone, so this a terrible but a potentially useable patch.

Steps to reproduce:
I haven’t been able to reproduce it. I can upload a reduced version of the PCB that causes the problems if given permission (I’m a new user).

KiCad version:

Application: KiCad PCB Editor x64 on x64

Version: 7.0.7, release build

Libraries:

wxWidgets 3.2.2

FreeType 2.12.1

HarfBuzz 6.0.0

FontConfig 2.14.1

libcurl/7.88.1-DEV Schannel zlib/1.2.13

Platform: Windows 10 (build 19045), 64-bit edition, 64 bit, Little endian, wxMSW

Build Info:

Date: Aug 14 2023 02:42:39

wxWidgets: 3.2.2 (wchar_t,wx containers)

Boost: 1.81.0

OCC: 7.7.1

Curl: 7.88.1-DEV

ngspice: 40

Compiler: Visual C++ 1936 without C++ ABI

Build settings:

KICAD_SPICE=ON

[m852]

open the project settings look at the design rules … maybe there is a minimum size limit?

[kbless7]

I believe I have everything set that I need to.

[kbless7]

Here is the PCB so that people can inspect the issue better.

test.kicad_pcb (655.0 KB)

[dsa-t]

This is fixed in 7.0 testing builds, see related issues:

Zone fill cause shorts (#15160)
Zone fill error (going pads no in net) (#15340)
Thermal spokes don’t properly connect to pad (#15476)

[kbless7]

Thank you, dsa-t. I think it’s a combination of #15160 and #15340. If I’m reading the links correctly #15160 should have been fixed in 7.0.7, but #15340 is scheduled for 7.0.8?

[dsa-t]

All of these were due to a bug in a library called Clipper2. The bug has been fixed and the library updated. The initial fix for #15160 only reduced the likelihood of the bug occurring.

These changes are currently in 7.0 testing builds, that will eventually become 7.0.8.

[davidsrsb]

Todays Testing includes the new clipper2 version and removes a workaround for an earlier bug.
Testing users please have a good look at things like zone fills and thermal spokes as clipper2 still has known issues and has caused several strange KiCad bugs in the past

[m852]

I noticed that this behavior usually occurs when checking boards made in version 6. Now I opened the board in a test assembly and the drs swears, although visually everything is in order

For the test, there is a small fee after running the test, the polygons are disabled (part ) Pay attention to the silkscreen especially the outline mode of the sensor
UV sensor.zip (105.0 KB)

[dsa-t]

This sounds like a different issue, please report it to GitLab.

[m852]

When refilling polygons or checking the rules, the track is disconnected from the site … Thermal barrier site is this related to this problem? Or is it the consequences of version 6?

[dsa-t]

Your problem is not related to the problem discussed in this thread. 7.0 uses 45 degree spoke angles for certain custom pads on your board, causing disconnects, 6.0 does not. This can be considered a bug. Bugs should be reported on the GitLab issue tracker, not here.

[m852]

Could you help me as I am writing through a translator and it is very difficult to correctly state the problem on gitlab? Since you fully understand what is happening in the example …