(Yet another) PCB layout without Schematic question

Hello Kicad people,

I am new to Kicad and I am looking at using it for designing some PCBs used for interfacing an IC to a test system. I need to regularly make these interface PCBs, for different ICs.

I have read many posts asking for the ability to make a PCB layout without a schematic. I understand that there are many who do not understand the need for this, but there are also many people asking for it.

My application is as follows:

  • The only components on the PCB are the IC and some connectors for plugging into the test system.
  • I need to connect every pin of the IC to one channel of the test system. All test system channels are identical so it does not matter which channel any given IC pin connects up to. Except …
  • The coupling between traces must be minimised. Each trace between an IC pin and a test system channel must be as short as possible and there must be minimal crossover of traces.
  • I do need to know, of course, which test system channel is connected to each IC pin. I feed this information into the test system and its software uses that information to know how to connect to the IC.

My approach with my existing CAD is to begin with a “template” design with the footprints for the test system connectors sockets already placed. I then design the IC footprint and place it into the centre of the board. I then make traces between the IC pins and the nearest (as yet unoccupied) connector pin.

After that I run a CAD system connectivity check which tells me all the “bad” connections I have made on my PCB design. I can use this as the basis for making the file which the test system needs to find each IC pin.

So far with Kicad I have been able to follow my design methodology as above until I get to the point where I try to do a connectivity check. The DRC report tells me that various pins have traces too near (it seems that this includes traces touching the pins), but it does not tell me anything about where the traces are going. I imagine that this is caused by the lack of a net database behind the DRC check. So I’m struggling to get a report that allows me to extract the connectivity such as, for example, that IC1 pin 1 is connected to PL1 pin 1, IC1 pin c is connected to PLy pin z etc…

If Kicad is just the wrong tool for this kind of (fairly simple) task than I would prefer to know now so that I can move on.

Thank you for reading this, and any helpful pointers or suggestions would be very welcome.


I’m seeing contradiction here or maybe I’m missing something?

KiCad may be right tool if you are willing to do some scripting with python. It’s not too hard to write very simple connectivity algorithm if all your traces terminate at pad centers and are continuous, as in each segment starts where previous ends, without gaps that may be hidden by trace width.

Hi qu1ck,

Thanks for your reply.

Maybe I didn’t make it clear enough …

With my existing CAD system (Seetrax XL Designer) I can use the connectivity report as the basis for making the file which the test system needs to find each IC pin. The report tells me that there is a connection between two pins, which does not correspond with the (not yet existing) netlist.

With Kicad I can get a DRC check report and it tells me, for example, that there is a trace too near IC1 pin x, but it does not tell me anything about that trace except the trace length. Also, as some traces go through vias, some of the lengths are quite short. So I can’t deduce the connectivity from the Kicad report in the same way as my existing CAD.

I’m not familiar with python but I regularly code in C and other languages so I expect it would be reasonably straightforward to look at scripting. I already have to do quite a lot of file manipulation - I usually use Excel to extract nets, pins etc, so there might be something more to be gained using scripting.

Can you point me in the right direction about where to look for more information on that?



Here is python API documentation https://docs.kicad.org/doxygen-python/namespacepcbnew.html
It’s autogenerated from comments and it’s quality is “meh” at best but it’s a decent starting point.

Best way is to learn by looking at other plugins and if you really want to get to the bottom you will have to look at kicad code.

Few pointers: look at BOARD object getters, specifically you are interested in GetModules() and GetTracks()

From modules you can iterate through their PADS and get their centers. Each track has start and end.
You will also have to consider which layer track/pad is on but ultimately it’s a problem of building a graph of connections between all track segments and pads and then printing that graph (or just connected pad sets) in whatever format is convenient for you.

Even you asking for not schematic…
According to my imagination you could make w schematic arranging the pads of test system (at schematic) in the same way as you have it in your “template”. Then designing a IC symbol with pads distributed as they are in real footprint. Then at schematic you could easily see how IC pads should be connected to test pads to have the connections short and simple. I don’t know if at schematic you are able to use wires at any angle but may be yes - it will simplify your task.
Then going to PCB and using advanced routing possibilities you will probably be able to make each track by clicking only twice (track begin and track end) and the whole track will be made for you.
Just check such solution.

Note that each track segment has a start and end. There may be a function that gives you a list of connected segments. If there isn’t, you’ll have to chain them together yourself. KiCommand (a plug-in) might help here, as there are functions that determine connectivity (see command connected). You might have more luck sifting through the Python documentation for BOARD_CONNECTED_ITEM. It’s not clear to me if KiCAD maintains the connected tracks as separate nets (identified through either a NET_INFO object or a net code (int)) if there is no schematic. I know the connected TRACKs are identified as nets if you have a schematic, I’m just not sure if separate tracks are separate nets without a schematic.

Actually D_PADS are BOARD_CONNECTED_ITEMs too so they also have a net.

Hi again,

Thank you again for your help. There’s a bit of a learning curve here, but it looks like I will be able to get KiCad to do what I want so I will persevere.

That’s the trouble with software. The real cost of software is not what you pay for it but the hours you invest to learn how to use it and in the data you spend so much time entering to make it work.

Best wishes,


Minus the hours and money which you would spend if you must do it without that software.

The learning curve can be dramatically reduced using schematic+swap_pins_plugin.

Labels are used in the schematic instead of wires.


Can you post a screenshot of a typical adapter board?

I am a strong believer of always making a schematic first.
You can not make a decent DRC check without a schematic or netlist.
With a schematic (and netlist) you also get the benefits of automatically walking around pads you do not want to connect to and accidental short circuits.
If your test jig has any fast signals, then signal integrity becomes a concern, you may want to add a GND plane, maybe some decoupling caps. Maybe you need some widert tracks for higher currents. Such things are all much easier with a schematic (and netlist).

You say your PCB is so trivially simple you do not need a schematic
I’d say that if the schematic is so trivially simple, it takes 2 minutes to draw it.
An easy way to draw such a schematic is to first put the IC and connector in the schematic and assign footprints, then put them into Pcbnew with F8 and start drawing tracks. Then, when you get near the pin you want to connect to temporarily stop, and then make the connections in the schematic first before continuing. You can have both Pcbnew and the Eeschema open at the same time.

Note from the screenshot below that KiCad prevents me from making connections to “the right” pads, but also from connecting to “the wrong” pads.
Because it automatically walks around the odd pins of the connector (and uses current default rules for track width and clearance.

For the schematic you can work either with labels or wires. (or a combination).
Labels have a very handy auto increment feature. If you draw a label that ends in a number, then if you hit the [Ins] key, another label with the next number is inserted below it. For example, this is the top part of a 40 pin connector, and I’ve labeled pins 2 through 40 by just pressing [Ins] and let the keyboard repeat.

I also assume the connector(s) to your test jig are in a fixed position, maybe also the board outline? If so, then making a template project may be a good idea.

If you really want, you can draw the PCB without the netlist with:
Pcbnew / Route / Interactive Router Settings, and then enable “Highlight Collisons” and "Allow DRC violations"

But then you also loose the clearance between tracks, because KiCad does not know where to apply the clearances. For me it’s a dark alley that leads into more trouble then it’s worth.

This is the project I made the screenshots from:
asdf_adapter-2020-05-27.zip (10.6 KB)

P.s. I put a STM32F100 in the schematic, and when you only deal with pin numbers, this is a bit of a nuisance, however, you can just as easily use a schematic symbol for any (44 pin) connector, and add the footprint of the LQFP-48 to it.

If you can post enough info to make such a adapter board, I’ll have a look at it, maybe make a complete version, and try to give some tips to help in your specific situation.

Hi all,

Firstly, thank you all for your contributions. I appreciate that it takes quite some time to write such detailed explanations. Also, I am a real newbie with KiCad and the concepts for how it deals with PCB design are taking me some time to get to grips with. At the same time I am trying to not constrain my thinking by seeking to achieve my goals using the same methodology which I have developed over years of doing these designs.

A screenshot of an example PCB (at the more complex end of the spectrum) is here:

This is a PCB with about 500 connections to the IC, which is a BGA with pins on an irregular pattern. The IC goes in a test socket which is why there are mounting holes present. A more typical application would have one to two hundred pins. Just to design and check the IC footprint for this example took more than one day, because the position of most pins was defined by individual X and Y co-ordinates. So you can see why I would be reluctant to repeat that process for a schematic which I don’t believe I need.

The main check which I do for these boards is a trace clearance check, which my existing CAD can do without any netlist. I also check that there is a 1 to 1 correspondence between the IC pins and the connector pins, which is possible on my existing CAD as I mentioned earlier. I use the report from this to generate a file for the test system, so it knows how to connect to the IC. If I need to actually specify connectivity (and therefore check it is correct), which sometimes happens in a situation where I don’t need to connect to every IC pin, I usually make a netlist using only the IC pins I need, let the CAD tell me which connections are there (which would count as errors at this point), and use that information to modify the netlist to add in the appropriate connector pins for each IC pin. I do all of the report checking and netlist manipulation using Excel and a plain text editor.

I decided to try KiCad out with a very simple IC (10 pins) and I was able to manually note which test system channels were connected to each IC pin in about 15 minutes including error checking / rectification. I then tried a more complicated IC with about 120 pins, but you chaps are correct to say that I am unable to do effective clearance checking and I am unable to get a report telling me how I have connected up the IC pins.

As for signal integrity, I don’t want to go into the details of the signals which come out of our tester, but we cannot tolerate any surplus stray capacitance or coupling between traces, so ground planes, controlled impedance traces and such like things are not allowed.

I hope this helps with your understanding of what I am trying to achieve.

Thanks again and best wishes,


Some beginners are struggling with the layout of a NE555.
Other beginners are seeking efficiency for 1000+ pin specialized test rig automation…

So not all beginners are created equal :slight_smile:

As you make multiple of these test rigs you want as much as possible of the process automated. This reeks of some kind of scripting approach.

Scripting in KiCad is … not my strongest point. I run Linux, and Pcbnew scripting has only recently been enabled (again) for Linux. Eeschema does not have any built in scripting at all at the moment, but apparently it’s being worked on for KiCad V6, which may be a year or so in the future.

However, because of the openness of the Open Source project which KiCad is, there are a lot of side projects and scripts around KiCad. (Although these tools have very varying quality and bit rot).

Some of the external tools for KiCad are listed on the KiCad website itself:

But a bigger list with external tools and scripts is on github:

One of the scripts that seems most applicable for your situation is: https://github.com/xesscorp/WireIt

In this: https://www.youtube.com/watch?v=-FPzxCktdcs video @ 04:40 it is shortly mentioned that one of the uses of WireIt is to connect an FPGA to connectors (with software configurable pins, so which pins goes where does not matter for most pins). The idea is to point at 2 pads with the mouse, and WireIt creates a netlist connection between those pads.
WireIt can also export a text file with changes to the netlist.

Do you have any experience with Python?
(If you don’t, you may want to learn it, as it seems to be the defacto scripting language nowaday’s (I’m not a Python fan, don’t like the language much, but it’s “acceptable”. Just one of those compromises in life.)

The Footprint Editor in KiCad has some built in scripts for generating Footprints. These scripts are accessible via:
Footprint Editor / File / Create Footprint
These Footprint Wizard scripts typically are a few pages of Python. I assume you have the coordinates for the pads in your big BGA in some digital format. Either text, spreadsheet, csv… With one of the Footprint scripts as example you can read the pad coordinates from a file and create (most of) the footprint out of it. This should make the creation of your footprint a lot easier.

If you are interested in commercial support for editing such scripts or custom made scripts you can try contacting:

Although you seem to be allergic to schematics…

The symbol in KiCad can be split into several units. A 500 pin symbol in a single unit it is a kind of madness.
The units can be split as the user wants: by function, by geographical position, all GND pins in a single unit, any permutation is allowed.
In my case, a 484 bga was split by function except fot the power pins.

With the schematic this is straightforward.

No need with a schematic.

None of these features is mandatory using a schematic.
As I pointed out before the swap_pins_plugin is a wonderful aid.

Learning a new tool requires some effort that pays off quite fast. If I couldn’t get used to the new tool I would keep on using my current tool.

I’m not againts KiCad to implement the features you need (though I think KiCad has other priorities). I’m talking only about the current features of KiCad.

Drawing a schematic for this 500 Ball BGA example is straightforward but not very useful, and a bit tedious, althouhg working with labels it’s pretty much straight forward with the auto increment function, and dragging (blocks of) labels to connectors.

But as I said before, a programatically / scripted approach seems more fit for this type of work. Among the list of scripts I mentioned earlier, there is also a project called Skidl. Skidl is a python library for generating a netlist from a script. I see it as a sort of VHDL equivalent for schematic entry. With a few lines of python and Skidl a complete netlist can be generated from a spreadsheet or text file.

It is scripting approached from another side as I proposed earlier.

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