Hi all,
Firstly, thank you all for your contributions. I appreciate that it takes quite some time to write such detailed explanations. Also, I am a real newbie with KiCad and the concepts for how it deals with PCB design are taking me some time to get to grips with. At the same time I am trying to not constrain my thinking by seeking to achieve my goals using the same methodology which I have developed over years of doing these designs.
A screenshot of an example PCB (at the more complex end of the spectrum) is here:
This is a PCB with about 500 connections to the IC, which is a BGA with pins on an irregular pattern. The IC goes in a test socket which is why there are mounting holes present. A more typical application would have one to two hundred pins. Just to design and check the IC footprint for this example took more than one day, because the position of most pins was defined by individual X and Y co-ordinates. So you can see why I would be reluctant to repeat that process for a schematic which I don’t believe I need.
The main check which I do for these boards is a trace clearance check, which my existing CAD can do without any netlist. I also check that there is a 1 to 1 correspondence between the IC pins and the connector pins, which is possible on my existing CAD as I mentioned earlier. I use the report from this to generate a file for the test system, so it knows how to connect to the IC. If I need to actually specify connectivity (and therefore check it is correct), which sometimes happens in a situation where I don’t need to connect to every IC pin, I usually make a netlist using only the IC pins I need, let the CAD tell me which connections are there (which would count as errors at this point), and use that information to modify the netlist to add in the appropriate connector pins for each IC pin. I do all of the report checking and netlist manipulation using Excel and a plain text editor.
I decided to try KiCad out with a very simple IC (10 pins) and I was able to manually note which test system channels were connected to each IC pin in about 15 minutes including error checking / rectification. I then tried a more complicated IC with about 120 pins, but you chaps are correct to say that I am unable to do effective clearance checking and I am unable to get a report telling me how I have connected up the IC pins.
As for signal integrity, I don’t want to go into the details of the signals which come out of our tester, but we cannot tolerate any surplus stray capacitance or coupling between traces, so ground planes, controlled impedance traces and such like things are not allowed.
I hope this helps with your understanding of what I am trying to achieve.
Thanks again and best wishes,
Paul