Work in progress: Native Altium Importer

@Seth_h @nickoe can someone of you start a windows build on the jenkins server to allow some testing?

I added support for netclass parsing and fixed a very bad bug (no bottom layer elements). Now I need to think how to go from altium design rules -> kicad design rules.

1 Like

You might consider waiting on this until we have the V6 design rules / constraints spec locked down (this is under active work right now). It should be able to map design rules from Altium that are impossible to implement in the current DRC system.

2 Likes

@GyrosGeier can probably help with the Windows test builds

2 Likes

@craftyjon when do you expect to have this integrated? I’m OK with ignoring most of the rules for now.

@Seth_h when do you think rounded traces are finished? I heard something like a week :stuck_out_tongue:. I think there is not that much missing until code-review can start. Having it merged would allow wider testing.

1 Like

No schedule yet, I’ll send you some more details

Yes, I have triggered a build and will link it later.

A windows build preview is available in https://kicad-downloads.s3.cern.ch/windows/testing/patched/kicad-patched-587-5.99.0-843-gaebd9d346-x86_64.exe

https://kicad-downloads.s3.cern.ch/windows/testing/patched/kicad-patched-595-5.99.0-850-ga17f8c705-x86_64.exe

2 Likes

I tried installing this patch build and it didn’t seem to install the binaries or kiface files for some reason. It installed a lot of other stuff though!

Hey @pointhi great work so far, this is quite exciting!

I built it for Mac (some fixes needed, I commented on the MR) and tried on a few work boards.
I’m pleasantly surprised how well stuff works already. Of course arc traces don’t work yet (and I use a lot of those in my Altium designs) but that is coming soon. Other than that there seem to be a few minor issues with zones and text. I can make test cases if needed and report issues in more detail on your MR.

I would suggest doing simple rules stuff first, to set a framework, and that can expands as V6 firms up.
If you can convert net-clearance rules, that should allow a DRC pass in KiCAD
Default net width could also be useful.

Also there are a number of things that are design rules in Altium but are not treated as such in KiCad (for example, zone settings), so it would be fine to import those for now, as we’ll have to adapt everything anyway in case we bring those under the “design rules” umbrella as part of V6 (this is not yet certain)

1 Like

That is indeed a bit strange. None of the exes are packaged either.
I think someone have been messing with cmake in kicad then. The patch job uses the following to install the stuff in a deterministic dir, and not reference a custom path on the build machine on debug output.

        -DCMAKE_INSTALL_PREFIX=${WORKSPACE}/_install/msys64/${BUILD_DIR_SUFFIX} \
        -DDEFAULT_INSTALL_PATH=${MINGW_PREFIX} \

Or maybe WORKSPACE does not resolve to anything

@craftyjon should be good now

1 Like

Updates of the last days:

  • Inital support of various dimensional elements
  • bugfix of arc calculation
  • some clearance rules are parsed for zones
  • plane layer should now work correctly
  • import of board outline

Next steps:

  • improve vias (blind/burried,…)
  • add support for board cutouts
  • add support for hatching in zones
2 Likes

@pointhi Do you prefer bug reports on the merge request or as a separate issue on our branch, or would you rather wait?

I my case, I am happy that you got around to fix the board outline, that was one issue I saw, another I would like to report is about a slotted pad. Thank you very much for your effort, it seems to work very well already! :slight_smile:

4 Likes

@nickoe I think reporting on the merge request is the better approach, to have everything documented in there.

It would be nice to have another windows build with the last improvements integrated, if you don’t mind.

3 Likes

@pointhi Yeah, I just triggered it when I posted, so it just had to build and upload, it is at:

https://kicad-downloads.s3.cern.ch/windows/testing/patched/kicad-patched-601-5.99.0-855-g4230bc599-x86_64.exe

4 Likes

Hi,
thanks for the build.
I gave it a shot today. Output Looks rather nice!

  • If there is a polygon/fill with keep out attribute checked in altium, KiCad import will turn it into board shape without on the same layer. So instead of copper keepout around mounting hole you have copper.
  • Designator orientation or position is messed up - in lot of cases it should be oriented vertically but it is imported horizontally
  • I have footprint with silk screen tented vias - this did not turned out well. But this is a quite corner case - creation of the footprint in altium is quite elaborate, not many people would do that.
    Hopefully I’ll be able to make a more thorough comparison during the weekend.

Cheers,
Jan

Unfortunately KiCad does not support a pad stack editor that would let you apply pad modifications (like whether or not to cover with soldermask or silkscreen) to individual vias, yet. So, some of the things from Altium will be “lost in translation” until KiCad has all the required features.

2 Likes

It’s not done at level of via. It’s done as a polygon in solder mask layer.
https://www.eevblog.com/forum/eda/via-tenting-in-thermal-pad/msg527114/#msg527114