Wires not connected with bus and hierarchical sheet on the way

[mariusz]

I found a case in which KiCad doesn’t see a connection where in my opinion there surely should be one.

Main schematic:

“Sub” sheet:

My expectation would be that KiCad sees that J4 should be directly connected to J2. However, it doesn’t see the connection here:

ERC too complains about them being unconnected:

(there’s also warnings, but let’s skip them for now - unless you think they play a role in the main issue)

Some things I noticed:

• if I remove the resistor and connect “OUT_0” directly to “VCC”, then I get the same error on this line too
• if I remove both “GND” parts and put a direct wire between “OUT_1” and J2 instead, then the problem disappears
• if I “unpack” the hierarchical sheet and place the content directly in the main one, then the problem disappears

So, there’s quite a lot of factors that have to occur all at once for this to manifest itself.

I’m wondering, whether it’s me still not understanding something, or it’s a bug in KiCad. I saw some threads about similar issues in the past, but they’ve been fixed in version 6.10. I use 8.0.2. and wasn’t able to find any similar report from versions 7+.

The zipped project:
repro.zip (15.3 KB)

Any suggestions appreciated

[paulvdh]

At the moment I’m a bit cloudy in the upstairs department and am not sure why your example does not work (I have not downloaded it).

Tin this older thread: Sheet pins and busses, partitioning the bus - #2 by paulvdh I posted an example I created that does rename buses and does work. Maybe you can figure out the differences from there.

[paulvdh]

When I remove the BUS1 wire + label + bus entry, and try to recreate it with the foldout function, I sometimes get a “Bus has no members” message.

But at other times it does recognize the two bus members and it works so the result is inconsistent.This appears to be a bug.

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Edit / A little bit later.

A right click on the section between the BUS0 exit, and the split off to the right does not even get the Unfold from bus option in the context menu. It only shows very few options.

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Edit / A little bit more later.

Even after deleting the bus (keep the bus label) and redrawing it, the BUS1 does not connect to the SUB_BUS1 bus member.

[bask185]

I think you should replace the _ by a . to create a prefix.

I just posted an example here, I haven’t tested it though.

Schematic hierarchial structure

If you look close at my example, you’ll see that the power sheet has no hierachial labels. I use global power labels. I did use hierachial power labels once. The idea was that I could see better where 12V, 5V and GND went to. But it didn’t improve readability that much and the power is often implied.Therefor I deemed that global power labels were good enough. how do I organise the sheets that they are in an “organised” or “logical” arrange? The main aim of hierarchial labels is readability …

This is one ‘sub’ bus.

[mariusz]

Thanks @paulvdh for your example. I think I managed to reproduce the issue in your sheet.

First, in Some_Sheet, I disconnected BUS_1 from the part and attached to GND:

Then I added a new terminal for VCC and GND, attached power flags

And this was enough to trigger the error on Truck_2, which is apparently (not) connected to BUS_1 on the opposite side:

Here your project as modified by me:
asdf_hierarchical-my-changes.zip (57.7 KB)

Regarding your answer, I’m pretty sure I created these connections using Unfold from bus in both the root and the sub sheet. Tbh, I often have a problem with unfolding from a bus, like you just showed. I usually “solve” that by clicking here and there, moving the bus a bit and then back, and after a while, unfold is suddenly possible again (perhaps should be reported as a separate bug…)

[mariusz]

Thanks, but it seems to not help. To be sure, I simply removed all underscores in all labels, but that didn’t change anything, the issue is still there

Edit: and if you meant that I should use “SUB.BUS” instead of “SUB_BUS”, I tried that too, without any luck. Also, SUB_BUS was meant to be an arbitrary name, not a prefix. In my main project, they have completely unrelated names.

[paulvdh]

I guess the post from bask185 is not relevant. It does create a difference whether you rename bus members, or create a named bus and use members, but the bus renaming such as you did does work. ( Edit: Renaming a vector bus like you did (without the dots) is legal, and also shown in several examples on: Schematic Editor | 8.0 | English | Documentation | KiCad)

But still, I am not entirely certain that renaming a bus like this is legal.

By inserting a resistor between OUT_1 and GND I managed to get KiCad to recognize the connection:

It’s also a recreation, because before I wanted to post a screenshot, I wanted to put the resistor a bit closer to the hierarchical sheet, so I dragged it towards it. And the result is that KiCad does not recognize your connection anymore:

On the PCB, the connection between J4 and R101 is still shows a ratsnest line (even after update).

After dragging the resistor and the GND symbol around a few times (left, right) I managed to crash KiCad twice. After some 10 more minutes of trying, I could not crash KiCad a 3rd time, but it’s definitely serious enough to create a bug report for this.

[RobK]

There’s a clue here, I’m sure:

[paulvdh]

On itself this it not a problem when a net gets renamed. Power symbols act as global labels and it happens quite often that multiple labels are connected together, and in that case KiCad has to change one of the label names. In such cases, KiCad issues a warning like that in ERC because it does not know whether the connection is intentional or a mistake.

But I do agree that it’s probably related. I guess KiCad gets confused somewhere between the bus renaming on the different sheets and the renaming because of the GND net. That was why I added R101 in the first place. But even with that resistor, the behavior is inconsistent.

[mariusz]

@RobK In my first example, the same warning also occurs for “SUB_BUS0” and “OUT_0”, but there’s no error on these lines.

@paulvdh thanks a lot for your trials. Yes, this issue seems to only happen when these specific elements are connected in this specific way. If you change pretty much anything (get rid of the bus, or the sub-sheet, the GND, the PWR_FLAG, or add anything… - and putting wires in place of the removed pieces), then it most likely won’t happen anymore. Putting a net tie just before GND could perhaps be an acceptable workaround for me .

But yeah, now I’m sure it’s a bug, so I’ll report it

[mariusz]

I’ve reported it as an issue: No connection with bus, hierarchical sheet and power symbol on the way (#18119) · Issues · KiCad / KiCad Source Code / kicad · GitLab
Let’s see what the development team thinks about it.

(edit: wrong link, fixed)