Vias Always Needed?

It is only fast after you have your production line tuned in (meaning invested quite some time beforehand.) Tuning in only stays valid as long as no parameter changes. For edging even the outside temperature can play a role. And if you do not do this for some time then you might have forgotten some key thing and invest half a day relearning everything.

I would also suggest never to be under such a short deadline as it will only result in failure.

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I respectfully disagree with all of @janvi points:

  1. Analog is harder to get right and in some cases harder to debug unless it’s a really basic circuit. Digital is a lot more forgiving and will introduce passives (resistors and capacitors) in a much more controlled manner. In particular I would NEVER introduce a beginner to mixed analog and digital it is a lot harder than it looks. Especially with regard to getting the grounding correct.
  2. Nothing wrong with mixing in large package SMD components. My very first design was TH TTL with SMD bypass caps and pullups in an 0805 package. Had no issues hand soldering these.
  3. Pretty much the default these days is double sided. The general rule of thumb is signal traces on the top and power traces on the bottom. But if already using THT why not use the bottom side for routing power and connecting the GND plane?
  4. The general rule is to have only horizontal (or vertical) traces on the front and the opposite (perpendicular) traces on the back connected with vias. There are plenty of introductory videos on Youtube demonstrating this technique with kicad.
  5. For a beginner I think the supplied components are in footprint and symbol libraries are going to be better (since they are vetted) than what a beginner can accomplish and will be less prone to error. It’s great to be able to create your own components but that should come as a last resort.
  6. Trace widths of 1mm (40 mils) are ridiculously too large. I would even say that for most low power boards the widest traces should be around 0.4mm (16 mils) for power traces and that signal traces should be around half that. With 1mm traces routing will be a nightmare. You’ll quickly run out of board space around components.
  7. This is totally wrong. You can have a 5 2-layer boards made and sent to you in less than a week for under $25 USD (which include DHL shipping). During the time of film cameras I had a dark room and developed my own film as a hobby but I could send to a lab, wait 5 days and get much better quality. Plus I didn’t have noxious chemicals I had to deal with
  8. Wrong again, modern EDA tools have design rule checks that completely mitigate the need to have to test for these issues.
  9. Never having a deadline means never finishing the project because of the need (especially as a beginner) to be constantly tweaking the design and thus never finishing it. It’s better to submit a design that is flawed so you can learn from your mistakes
  10. Again forget about this and just use double sided and commercial fab houses from day 1. It is no longer 1989. No way do I want to go back to building kitchen table PCB’s. If the digital circuit can run at low frequencies then build it on a breadboard or stripboard first. Then move your design to a PCB
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This mostly done in two layer designs as it allows having a ground plane on both layers and then stitch it together to create something as close as possible to a single uninterrupted ground plane. (Vias have a certain cost regarding EMC so one might not want to switch layers too often. Especially not for critical signals.)

The alternative is to try and avoid having traces on the second layer and get a near uninterrupted plane on the other (This is sometimes possible if you have a single specialized chip with a good peripheral layout that allows routing to the external connectors and passives without crossing points.)

I agree that it help facilitates an uninterrupted ground plane. It also makes the layout easier and reduces cross-talk. Layer switching and vias for signals don’t become an issue until you are working with higher frequencies (like 50mhz and higher) when via inductance tends to dominate. It’s also all too easy at higher frequencies to unintentionally create patch antennas with vias which is bad with regard to EMI. At lower frequencies that most people work with (I suppose around 10mhz or so) I don’t think one needs to worry so much.

dU/dt and dI/dt of slopes are bigger problem then frequency. Continuous cost reduction because of competition makes the same type ICs produced 20 years ago are now produced in much smaller (cheaper) technologies meaning lover capacitance with the end effect of even 10 times faster slopes. If you read a pdf of digital ICs you will find the max time for slope but not the minimum.
It happened that we did the connected by small cable adaptor for some educational system to program serial EEPROMs. When 10 years later we bought the same type EEPROMs they didn’t worked in our adapter. The EEPROM output slope was so fast that crosstalked to CLK line makeing EEPROM seeing more clocks than it should see. First the slope was so fast that crosstolked, second the CLK input was so fast that a much shorter pulse than specified in datasheet was accepted as next clk pulse.

If the rounded rectangle features in copper layers are flashed then there should not be any issues. Globally increasing should increase both these features. Yes, there will be an issue with the rounded rectangle feature if in copper layer they are not in flashed mode.

Via and component holes are PTH which restrain copper plating on hole barrel to create connectivity/continuity between top and bottom layers counting inner layers if it’s a multi-layer PCB.

It seems with all threads, a reasonable question get asked, a reasonable and applicable answer may or may not be given, then everyone (myself included) let the topic wander off* as we debate minutia which likely doesn’t apply to the original question. We also drive off the original poster as he may not have gotten a good answer and certainly is lost by wandering topics.

I’m not griping, just observing we may not be acting in the best interest of the original poster.

In the autopilot world, we called this a slow over.

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