Some time ago I was discussing zone arficat similar to the one indicated by the arrows in the original screenshot. In my case, changing the Zone fill strategy from “Smoothed polygons” (default) to “Mimic legacy” improved things. You can try to change this setting and check if it works for you.
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@fred4u, I tried that but it made things worse as some areas did get no more filled. BTW, I will call my artifact cat in the future arficat 
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I am quite impressed with the way KiCad draws line segments around clearances.
In the screenshot below the orange line is the clearance around a THT pad and the blue is the generated edge of a zone (which is set to the same clearance).
KiCad retracts the control points of the lines just enough that the center of the lines do not cross the clearance, and that extra distance is the 5 micrometer specified in the default settings. That is also what flum has flagged in his first screenshot. The oval areas indicated are where those retracted lines of the circle blend with the straight lines.
So I stick to my opinion.
If this causes the PCB to be put into a more expensive process by his PCB manufacturer, then he is simply cutting it too close and Giving KiCad not enough room.
Heck, it may be that the PCB is perfect (apart from having real arcs) but the PCB manufacturer is making rounding errors. KiCad works with nanometers, which is probably a higher resolution then what a PCB manufacturer can manage. Rounding errors because of truncated resolution (improper use of “floor()” or “ceil()”, metric / imperial conversion) can easily happen, and often it’s easy to build in some tolerance in your design rules to accomodate for this.
Some time ( a year, maybe more) ago there was another issue about tolerances. It was a QFP chip with a 0.5mm pad pitch and either the tracks, or the pads (Width + Clearance) matched that pitch perfectly, and it worked, until the footprint was rotated. Then it got flagged by DRC. It was “fixed” by adding a 1nm tolerance into the design rules.
The ideal way to avoid this problem would probably be to use real arcs instead of segment approximations in zone filling. Bezier curves should still be approximated with arcs, but that would hardly be a problem with copper and DRC because bezier curves aren’t usually used for the copper.
Maybe it would still be possible to run into the same problem in tight places where there’s very little room to fill a zone (the arrows in the original screenshot), but at least the circled areas in the screenshot shouldn’t be a problem anymore.
There will always be rounding errors.
I just drew a line with a length of 4mil, and kicad also shows it as a length of 0.1016mm (so two digits of precision are not shown)
You also have a very limited influence of how a PCB manfacturer mangles your Gerber files. The only real solution is to build in a tolerance, so rounding errors are harmless.
Sidenote:
I have a thorough dislike for bezier curves. Arcs are superior to bezier curves in several ways.
- They go right through their control points.
- They are mathematically simpler.
- Easier to use on CNC machines (almost?) all support arcs.
With a few tangential arc segments you can draw surprisingly smooth curves.
The trick is to have software with good support for calculating arc radiuses for the arc fitting.
To do it properly quite a bit of math is needed.
The technique is called “bi-arc”.
I disagree with paulvdh that the indentations at the arrows are generated by the segments that hug around a circle. In this screenshot, I increased the ‘minimum width’ of the zone just enough (0.209) that the 0.2mm gap between two regions is still connected* (was typo: disconnected), and it looks like there are two blobs overlapping. What you see in the OP image is the same, but the overlap is just much larger. The only explanation I have for this is that the fill algorithm has the exact round-off errors that you explain.
btw, my gap is exactly 0.2mm, and a 0.2mm trace can pass through without DRC violations, and in the next screenshot the zone is set back to exactly 0.2mm. In legacy mode the zone fails to squeeze through and I get an unfilled island.
Mmmm, definitely something going on, I made a quick test with a double row pin header and a zone, the gap in the Y direction is different from the gap in X direction…
same effect seen in the gerber files:
Application: KiCad PCB Editor (64-bit)
Version: (6.0.1), release build
Libraries:
wxWidgets 3.1.5
libcurl/7.78.0-DEV Schannel zlib/1.2.11
Platform: Windows 10 (build 18362), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
Date: Jan 15 2022 13:36:27
wxWidgets: 3.1.5 (wchar_t,wx containers)
Boost: 1.76.0
OCC: 7.5.0
Curl: 7.78.0-DEV
ngspice: 35
Compiler: Visual C++ 1929 without C++ ABI
Build settings:
KICAD_USE_OCC=ON
KICAD_SPICE=ON
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This is a separate issue. If you look closely, the bottom of the circle is flat and the left of the circle contains a vertex. This is probably emergent behavior from the “Max allowed deviation” setting resulting in a number of vertices around a full circle which is not divisible by 4.
What is (very likely) happening here is:
- KiCad modifies the intermediate points of the line approximations. It shifts them outward by (default) 0.005 mm. to make sure that the middle section of those lines do not violate the clearance.
- This reduces the “copper width” between two pads by twice that “max-deviation-value”
- der.ule sees different gaps. Very likely this is because the number of line segments created to approximate an arc is (in that instance!) nit divisible by 4. different angles of contact result in different rounding artefacts. (Edit: Just read Zom-B’s post. I came to the same conclusion independently).
- If the width of copper is bigger then the “minimum copper width” plus twice this “max-deviation-value”, then the interaction between the different pads is gone.
Thank you for checking that.
I was wondering what the Gerber output would be.
That the Gerber and the PCB look the same gives me confidence in the consistency in KiCad.
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I can confirm the ‘rough edges’ disappear after decreasing the ‘Mininum width’ of the zone by the same amount of ‘Max allowed deviation’. The copper gets thinner this way and may result in the same fab mis-classification as OP was troubled with. This means that one should always design features larger by at least the amount of ‘Max allowed deviation’. i.e. if the fab requires 0.2mm width and clearance, you should use ≥0.205mm minimum for both. That is, both in the zone properties, and clearance in the pad, hole, and track properties (copper of pads, holes, and tracks can be exact, as this has no interaction with zones)
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The same goes for zones within zones. I’ve had a number of zones where I needed to increase the clearance by a small amount as I had a handful of clearance violations from zones with higher priority against zones with lower priority by using the minimum clearance allowed according to the design rules. Does this warrant the filing of another ticket?
If you have a reproducible case, then yes I think it warrants a ticket.
In other news I’ve made some opitmizations the greatly improve the divots at the ends of arcs (but not the divots between holes). It just went in so if anyone wants to try it out you’ll either need to build yourself or wait for the next nightly.
@eelik was there an issue associated with this?
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Not really. I suggested Real arcs (circular segments) in gerber export (#4651) · Issues · KiCad / KiCad Source Code / kicad · GitLab as a solution and the first case was attached there, but these cases mentioned here are bugs which real arcs won’t necessarily fix as I have realized. It’s of course possible that if someone implements real arcs in zone fills it fixes the problems as a byproduct.
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