Sounds cool.
That sounds a good idea.
You may also find useful the attached python file that generates a NET report from a PCB design, ( in PADS Ascii format - easily human scanned and version checked)
This would allow a design with multiple NET sources (any mix of SCH and/or multiple scripts), to save a PCB snapshot for verify of critical NET changes.
PcbNew_Export_PADS_NET.py (20.6 KB)
Have you seen QEDA ? Just saw this mentioned in another forum..
It uses YAML ascii files, to describe both SCH and PCB symbols, in Text files.
leads to the ASCII file part descriptors
https://github.com/qeda/library/blob/master/hirose/df13a-6p-1.25h.yaml
This would allow you to use any mix of Graphical and Text-File flows, for NET sources and Library sources, right up until the PCB layout itself.