Understanding Pad and associated details


I’m just starting in Kicad, coming from using design services. I want to make sure I fully understanding how Kicad controls pad sizes etc. Please look at the below and let me know if there are any mistakes or misconceptions.

  1. Drilled hole, specified in footprint library else modified in PCB Editor hole by hole.
    No “automatic” rule exists (like for solder mask relative to pad OD)

  2. Pad OD: pretty much the same as for Drilled hole.

  3. Solder Mask OD. Calculated by the pad OD + 2 x Solder mask clearance
    Specified in: Setup / Pad to Mask Clearance: Solder mask clearance.

  4. Keep out area around pad. If another pad or trace falls into this area an error is generated (DRC)
    Defined by “clearance” value in Setup / Design Rules / NetClasses Editor.
    Applies to traces as well.
    Traces are defined to a NetClass in the routing mode by selecting a track then pressing “E” on the keyboard

Specified in the footprint.

The hole diameter specified in kicad is typically the final hole size as you receive the board.
This size depends on the size of the component lead. (Rule of thumb: 0.2mm larger diameter compared to the maximum lead diameter)

Specified in the footprint.

The pad diameter is normally quite a bit larger than the hole to allow for soldering. There even is a minimum size increase specified by your manufacturer. (minimum annular ring.)

clearance can be specified on the pad, footprint or project level.
(pad setting overwrites footprint which in-turn overwrites project settings. Setting the pad or footprint settings to 0 means take the one of the level above.)

You only get an error if the other trace or pad is assigned to a different net.

And yes this clearance is defined on a net by net basis via the netclass. But it can also be specified at the pad or footprint level.

More details see: Tutorial: How to make a footprint in KiCad 5.1.x (From scratch)?

Hi Rene,

Thank you for the quick and detailed reply. Especially the link. I looked in the help file but didn’t think about the FAQ’s.


This issue trips up many users.

I recommend setting the Pad to Mask Clearance to ZERO; but it will depend upon the fab house you use and the color of the solder mask that you specify (for each fab house).

The ugly issue is that there will likely be at least one trace to that pad. The soldermask layer is a negative layer, meaning that any/all traces to that pad will NOT be covered by the soldermask.

I may be confusing your wording, however I’ve been the engineer on many many PCB designs and the solder mask has always covered the traces and vias. Perhaps I am missing you intention?


This may be one of KiCad’s idiosyncrasies.

Your OP image stated “Mask ID (3)” and the arrow pointed to the OD diameter of the soldermask clearance.

My first reply was based upon the information you initially provided.

The best way to gain understanding is to upload small portions of actual KiCad screen-grabs.

OK… the screen grab I uploaded was a simple graphic I drew to print it out and help me internalize the pad graphics I see in Kicad.
I think more graphically than verbally.

But thanks for the tip, I will definitely check the Gerbers before sending out for fab.

The 3D viewer in KiCad is VERY GOOD.

It is not a substitute for final Gerbers sent to a Fab.

Change some of the settings and check out how the changes affect the view in PcbNew, the 3D viewer, and the Gerbers.

@JohnRob The workflow suggested by @Sprig might work for hobbyists who do not really care how they receive their boards.
(And especially: Who do not care about accountability. In a company one important question is “Did we screw up or did our supplier screw up”. If your design files violate specifications of the supplier you are always the one who screwed up.)

The problem with that workflow is that one relies on the fab guys to set the correct clearance and min width settings and recreate the mask layer. (They specify a minimum clearance for a reason, they will not manufacture a board with your settings of 0.)

One problem that can easily occur is that you suddenly loose mask on fine pitched smd parts. (They increase the mask clearance -> now the remaining mask violates the min width settings)

My suggestion therefore:
Setup the mask clearance as specified by the manufacturer of your board. Do not go to the absolute minimum they specify if not absolutely necessary. That way your gerbers will define how the board will really look like (of course there will be tolerances.)
Meaning you are far more likely to spot problems your self when compared with a workflow where you rely on your fab.


The solder mask is the physical substance on the pcb board. The solder mask layer in KiCad is negative, the colored areas tell where the physical solder mask is not applied.

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This might also be a good read: What is the meaning of the layers in pcb_new and in the footprint editor?

Thank you for your post, I hope others read it and understand that minimum != standard. I have (had) to constantly remind our design service (and engineers) that traces should never be at the minimum unless there is NO alternative.

For this project I plan on having the boards fab’d by OSHPark. I have already entered their recommended settings (and rounded the minimums up a tad).

In my case, I’m very familiar with checking Gerbers, it is Kicad I am learning and because now I am operating the software myself I can no longer just provide requirements but have to actually implement them. Hence my questions on how / where the parameters are specified.

This brings up another question. I had to “neck down” a section of a trace. I accomplished this by simply selecting that segment and editing the width. It seemed to work fine. Is this the accepted method?


Sadly KiCad right now has no better option for neckdown than the one you used. I think this is something planned for the long term.

I clearly stated that it :

I’ve used “zero” for several OSHPark boards, and some really friggen small parts with excellent results.

My current reasoning is that other items on the board, such as plated through holes, are set to what the finished size is wanted, and the fab determines the actual drill size and method of plating to end up with a finished hole size. Once I found out that the solder mask color affects the Pad to Mask Clearance, I gave up trying to predict how each fab house might or might not tweak the design just based upon color of mask alone. I figure that it is their problem to adjust their manufacturing to get the final clearance that I specified.

Not all fab houses will do this for a design however. And, that means that different gerbers will likely be needed if a different soldermask color is selected for the next run of fabrication of the same board design.

The neck down process was not an issue.

I’m not being argumentative but why would you specify a clearance different that the fab house suggests? Even if you’ve had good luck in the past, I don’t see the benefit.

Once I found out that the solder mask color affects the Pad to Mask Clearance, I gave up trying to predict how each fab house might or might not tweak the design just based upon color of mask alone. I figure that it is their problem to adjust their manufacturing to get the final clearance that I specified.

I agree, the design files or Gerbers should reflect the final part. It is the fab house’s responsibility to make any adjustments needed to fit their process. But I am still not sure why you would set the “the final clearance” to 0.

If I found a fab house that did not make any adjustment to the gerbers for the process they use which resulted to boards not to the requirements… I will stop using those vendors ( and not pay for the boards).
I will admit, my past experience has been with industrial fab houses (some in China), perhaps the “hobby” market is different. We’ll see how OSHPark does :slight_smile:

Is friggen like 0402?



Thanks. In this case the neckdown is not an issue, its only there to made a ground connection that will be covered by ground plane.

However It might be nice for the DRC to generate a warning that a segment violates its NetClass specification.


What happens when parts and pads get small?

This is a KiCad library footprint: Package_SO:MSOP-8_3x3mm_P0.65mm. In the image I have changed the Pads to Mask clearance to 2mils as OSHPark recommends on their web page. As can be seen from the snippet of the 3D model, the soldermask between the pins is really small.

The math suggests that, with the soldermask clearances as above, the width of the soldermask between the pins is a little less than 4mils. I’ve seen where individuals have posted their results online where they push the limits beyond the OSHPark settings. And, it turns out that anything less than 4mils soldermask width was inconsistent.

It is my opinion that a little extra soldermask over the copper pads makes for less of a hand soldering effort than if there is no soldermask between the pins.

ON EDIT: I had this board fabricated by OSHPark with the clearance set to zero and the footprint worked just fine. I was a little surprised at how well it was done because it really seems stupid small to me.

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