Design is (almost) ready to order at PCBWay.
I have made the design in KiCad version 7.0.9 and I have a silkscreen logo that is covering many via holes.
I have read that we obviously don’t want the silkscreen covering the copper part of the via holes and when making the gerber files (Files/Fabrication Outputs/Gerbers…), I have checked the box: Subtract soldermask from silkscreen.
But when I use Gerber Viewer 7.0 to view the gerber files, the silkscreen file looks intact (i.e. without holes as I would have expected).
So how do I ensure that PCBWay does not print the silkscreen over the copper part of the via holes?
I asked in the PCBWay chat if they take care of this automatically, but they just said that they normally don’t fix customers files.
Also Google and ChatGPT was no help.
Are you sure that the vias must be exposed?
My vias are always covered with a solder mask and of course if I have any inscriptions on the overlay side, they are also on the vias.
Unless you are confusing vias with padstack ?
Normally vias are tented so will be covered by soldermask as stated above. There will be a slight bump in the silkscreen but definitely it can be printed. The setting you found is for bare copper pads.
I don’t know where you read that, but there is no limitation for this. Normally vias are covered by solder mask, and there is no limitation of also printing silkscreen over the copper part of the via. Maybe you mixed up via’s and pads. Pads have a cutout in the soldermask to be able to solder to the exposed copper, and that does not work if you print silkscreen over the pads. And this is what the Subtract soldermask from silkscreen. does. You only see the difference for pads, because via’s don’t have a soldermask cutout.
Via’s are usually “tented”, or (easier) the solder mask just printed over the via hole too. With small via’s this (mostly) fills the via hole but it will not always be level with the surface. There is no harm in printing silkscreen text over that but the text may be more difficult to read, especially with small texts.
I am a PCB beginner, so I may have made some bad choices or used wrong terms.
My idea is that the part of the PCB that has the silk screen logo on top of it consists only of vias that are not connected to anything. It will act as a simple perf board for prototyping and the user of the finished PCB themselves will solder through-hole components to the vias/holes and do their own connections with wires.
The term padstack is new to me and it may well be that this was what I needed as opposed to vias (not sure if the term via only makes sense if it also includes a copper trace, which my vias do not have).
But vias was the first thing I found in KiCad and it looked like a normal perf-board hole, so I went with it.
Should I not have done that?
My expectation was that the hole/via could be used as any hole in a perfboard with copper on both sides of the hole.
Ah, vias are not what you want for your use case then. Vias are often filled and normally used to connect between copper in different layers. And they are usually small, not for putting component leads through. See here: Via (electronics) - Wikipedia
If you want to make a perfboard, then what you want are TH (through-hole) pads.
Your next major stumbling block is: you cannot just place a pad on a PCB. The pad must be a footprint.
To make a pad as a fooprint you have two choices:
1/ Create a footprint that is a single pad.
2/ Adapt a footprint that is already a single pad into just the single pad. eg. Pin D1.0mm in the Connector_Pin library.
Right Mouse Button > Properties or Hotkey E then modify and rename the connector pad footprint to suit. Don’t forget to remove the 3D link.
If you want many; use the Duplicate function. RMB then Duplicate or Hotkey Ctrl + D.
Back to 1/. Create a footprint.
If you haven’t already done so; create a Personal Library.
Create a footprint in your Personal Library called “whatever”. Place and modify a pad to suit in that footprint. Save.
@jmk You’re mixing up schematic symbols and footprints (on the PCB) Schematic symbols do not have pads, but they have pins.
KiCad also has a few test point schematic symbols, and a whole library with different test point footprints. But it is also easy to create a footprint which just has a single pad, and no extra (visible) graphics at all. Connector footprints tend to have a lot of silkscreen lines, and test points have silkscreen text, so modifying such a footprint (make a copy into a personal library first), or creating a new footprint is the way to go.
The library management itself has a bit of a learning curve, but creating a new footprint with a single pad is extremely simple.
Then you can easily:
Put a test point symbol on the schematic.
Assign your custom footprint to it.
Make a copy so you have two of them, then copy into 4, 8, 16, etc…
Put them all on the PCB with [F8].
Place them wherever you like.
If you want to make an perfboard area, you can also easily create a footprint which has an array of pads. Or you can make a few footprints with small arrays of pads, and combine a bunch of them on the PCB to build up bigger area’s. This is especially handy when the available area has an irregular form.
Many thanks to everybody for clearing up my misconceptions about vias and for pointing me in the right direction.
Quite and active and amazing forum.
TLDR: I got it working thanks to your help
Longer version:
I now understand that the holes in a perf board that have copper for soldering through-hole components are not the same as those I can get from the KiCad PCBEditors’ button called Add free standing vias, which I had used extensively in my first design.
It sort of looked the same (after increasing the diameter and hole sizes), but then I had the problem with the silkscreen logo covering the copper part, which led me here.
Even though I had hoped to remain in the PCBEditor in order to avoid climbing the learning curve of the other editors, this was not to be.
So I followed your recommendations and created a (global) personal symbol and footprint library.
I then used the footprint editor to create a new footprint where I added one pad where I removed all the text that were on the silkscreen or FAB layers (e.g. REF** and name) so only the pad itself was visible.
Copying this to the PCB editor using the clipboard gave DRC warnings, so I added one of the newly created footprint design using the A shortcut (Add footprint) and then used the Add array function for multiplying the pad as many times as I needed (checking the ‘Keep existing reference designators’ option).
After reading your recommendations once again, I see that I did not follow the recommendation about going through the Schematic Editor and ; I went straight from the Footprint Editor to the PCB Editor. I hope this does not give me problems later on (this design has no components and the Schematic Editor is completely empty).
To get rid of more clipboard DRC warnings, I also had to redo my silkscreen logos and add them as footprints instead of copy/pasting them directly from the KiCad Image Converter tool. It was strange to me that KiCad supports the clipboard copy/paste functionality but then gives DRC errors when using it. But I solved it in the end.
I now have gerber files that has holes in the silkscreen where I expect it and also where the copper part of the pads are not covered by the silkscreen, which is great.
I believe I can now order my first small batch of PCBs.
Thanks to all for contributing to my KiCad journey
In order to avoid further DRC warnings, I also had to add unique nets to all the 34 places where I connected some of the pads (like on a breadboard). Tedious work, but that got rid of the DRC warnings
A minor detail:
When I check the KiCAd 3DViewer, my silkscreen logo is still covering the copper part of the pads (not the holes though). I am wondering if this is a bug in the 3DViewer.
But since the gerber files looks ok, I am not bothered with this. The uploaded image shows this issue.
Connecting tracks to the pads of these footprints will be a nuisance when these footprints do not have corresponding symbols in the schematic to create the netlist. And this results in:
This is yet another example of people making it difficult for themselves by wanting to skip the schematic step. It’s easy to put a symbol on the schematic, assign a footprint, and then duplicate it a bunch of times (Possibly Including wiring). Maybe you can also make use of the “Wire It” plugin.
So, what are the DRC violations you get? There are many different ones, and it does not mean there would be anything wrong by the footprint itself.
Also, if you do create a schematic, then make sure that during PCB Editor / Tools / Update PCB from Schematic [F8] you turn off the setting for Delete Footprints with no Symbols option.
It’s not a bug, it’s a feature. See: Preferences / Preferences / 3D Viewer / General / Board Layers / [ ] Clip silkscreen at solder mask edges.
Yes, the next time I will go through the Schematic editor from the beginning
And hopefully become a more skilled amateur pcb designer in the process.
I have made a note of checking up on the Wire It plugin and the Delete Footprints with no Symbols option.
The DRC violations I got when copy/pasting instead of using Add footprint were:
Copy/pasting from Image converter - Warning: The current configuration does not include the library ‘’.
Copy/pasting pad from Footprint editor - Warning: The current configuration does not include the library ‘clipboard’.
I know that warnings are not errors and that some warnings can be ok.
But since I am a novice pcb designer, I prefer to have no or few warnings; at least until my knowledge increases.
Good to know about the 3DViewer setting Clip silkscreen at solder mask edges.
Now my 3DViewer looks like I expect
That seems easy to fix.
You can use PCB Editor / File / Export / Footprints to New Library to create a (project specific) library and put the footprints in it. You also have to change this in the schematic, because that is the source of the information in KiCad. You can do this with: PCB Editor / Tools / Update Schematic from PCB, or directly in the schematic editor if you only want to change one or a few footprints.
I have done a fair bit of programming in both C and C++ and am used to spending some time to fix error messages and warnings. Even when some of them do not make much sense in themself, you have to fix them to prevent you from wasting time by reading them again and again, and for shortening the list so they do not obscure more important messages. And just as with compilers, in KiCad not all checks and error messages make sense in all situations. A common warning is: “Warning: Footprint ‘xxx’ does not match copy in library ‘…’.” This is a warning that can be very important for people using database libraries, but for some other use cases it does not make much sense.
KiCad has several functions in place to decide how to handle DRC violations. You can right click on any of the DRC violations in the DRC dialog and choose one of the options from the context menu:
The: Edit violation severities… goes directly to: PCB Editor / File / Board Setup / Design Rules / Violation Severity for a “permanent” setting, while the “Exclude”, “Change”, and “Ignore” options are marked and saved in some way and can be undone later. Experiment a bit with these options to make yourself familiar with them, and then decide for yourself how you want to manage each DRC violation in your project.
It may also be a good idea to disable a bunch of them now to remove distractions from your project, and then put them on a checklist to do before the Gerber files are sent out. With the Import Settings from Another Board button in the bottom of the DRC dialog you can import (specialized) DRC settings, for example from an otherwise empty “template” project which is set up for this.
