SKiDL: a Python-based schematic design language

[PCB_Wiz]

@Joan_Sparky

I remember that discussion and some of you guys were pretty enthusiastic about it.

Who, us ?

@devbisme

A few months ago, there was a discussion thread about editing/creating netlists directly as input for PCBNEW. I’ve been working on a Python package called SKiDL for doing just that. You can read about it here. You can install it here. You can hack it here.

Wow, that’s looking cool.
Some minor suggestions -
Can generate_netlist have the NET format name included ?

I can see this being used across many NET formats, including of course, kiCad.

I find this harder to scan visually
ERC WARNING: Unconnected pin: POWER-IN pin 2/VSS of PIC10F220-I/OT/IC1.

so maybe put the pin NumName first ?

ERC WARNING: Unconnected pin: 2/VSS POWER-IN of PIC10F220-I/OT/IC1.

Other comments -
Somewhat related to this, I have a small Python script that can export NET info from PCB-New.
Currently in test format, it exports in Mentor PADS Net format, in order to give an integrity pathway check for PADS → KiCad translator