Hehe, that was going to be my next question … 
You could also add some simple naming rules to SKiDL, to allow Append Board type merge ?
(Mentor has a similar ASCII-In Superset feature)
Provided there are no collisions on RefDes, and local net names are unique, and common net names are agreed on (GND,+5V etc) this append/merge should work well.
I think that just needs a RefDes offset (eg R100+, rather than R1+) and some unique local-net-name seed ?
We could also just insert the new netlist into the existing one. SKiDL will automatically disambiguate reference designators and net names.
Do you mean SKiDL manages the merge ?
Doesn’t that then require SKiDL can read as well as write the various supported NET formats ?
I was assuming the appended board would be in KiCad netlist format. If we wanted to merge arbitrary netlist formats then, yes, we would need some way to convert them into a canonical netlist format. But once in that format, just a simple program to insert the components and nets and SKiDL would probably handle it. You would probably want some control on when SKiDL keeps similar nets separate with a rename or when it merges them.
Now that I’mthinking about it, you could convert an arbitrary netlist into SKiDL code and then just execute it at the end of another SKiDL program. That would effectively merge the netlists.
Yes, that was what I was suggesting with the unique local-net-name seed suggestion above.
I’ve seen things like prefix $$$ or NN used to denote ‘local nets’, and anything else is considered global/common (GND etc)
This does vary by CAD tool, which is harder to manage.
I was thinking user offsets/seed would be simpler, and not require too much additional work in SKiDL, but be workable in most use cases I can imagine.
Yes, I see now. We could use either offsets or prepend a unique string onto refdes and net names to disambiguate. In any event, yes, appending one netlist to another with controllable merging is possible.
I’ve released SKiDL 0.0.3. The major change is the inclusion of the netlist_to_skidl command-line utility that converts a netlist output by KiCad’s EESCHEMA into a Python/SKiDL script. That’s useful when converting existing designs or crafting small building blocks for inclusion in a larger SKiDL-based design.
Once again, read about it here, install it here, hack it here.
I’ve released SKiDL 0.0.4. The major change is that the netlist can now be output in XML format. This allows external tools (like BOM generators) to work with SKiDL-based designs. I’ve tested it using KiCost to generate costing spreadsheets for some of my designs.
I’ve released SKiDL 0.0.5. The major changes are:
The library search list is now configurable. (By default, it searches the current directory and the KiCad symbol library directory.)
The search function now scans the part name, description, and keywords to find matching parts.
SKiDL 0.0.7 is out there with changes primarily to improve the installation process.
@devbisme I want to use skidl but I’m worried about possibility of refactoring. What happens when I change the script, create a new netlist which has different designators and import into pcbnew? I’m thinking that it will break the circuitry if I do that. Do you have any suggestions to prevent this from happening?
You’re right. SKiDL scripts don’t have a way to store a unique, unchanging code for each netlist component so it can always be associated to a component in the PCB layout. KiCad schematics assign a tstamp to each component for this purpose. I can’t do that with SKiDL because it generates the netlist anew each time the script runs. There’s no place to store tstamp-like objects in the script (particularly for iteratively-instantiated components). The only tentative solution I’ve come up with is to do graph-matching with the previous netlist and then relabel the new netlist to preserve the pseudo-tstamps from the old one.
This seems like a very nice capability. As a python obsessionist I am excited.
What is the status of this project?
The Xorn project by Roland Lutz is a python library designed to allow manipulation of schematics, netlists and other EDA data; it may be relevant/of use, since code exists in the wild to export gEDA data to eeschema netlist formats.
http://hedmen.org/xorn/doc/api/html/index.html
Regards,
Erich.
Together with KiPart, SKiDL is definitely my favourite KiCad companion, well done indeed xesscorp
One killer feature for me (if not already in the works/thinking) would be panelizing of gerbers as a last step of the whole SKiDL workflow/api. I’m currently using a SVG/Inkscape hack to panelize my boards when baking them at home:
$ cat crop_svg.sh
#!/bin/sh
inkscape -g -f `pwd`/kicad-plot-SVG-F.Cu.svg --verb=FitCanvasToDrawing --verb=FileSave --verb=FileClose --verb=FileQuit
Combined with a simple HTML file in dire need for Jinja2/templatization:
$ cat panelize.html
<html><head></head><body>
<object type="image/svg+xml" data="kicad-plot-SVG-F.Cu.svg"></object>
<br/>
<object type="image/svg+xml" data="psone_grafitti-F.Cu.svg"></object>
</body></html>
I have little clue how easily hackable gerbers are to achieve the same goal (panelize), but since the topic has been brought before on kicad forums I thought it might be a nice wish, combined with proper/automated management of mouse bites between boards, it can really be a huge time saver for both users and fabs, IMHO.
I’m glad that KiPart and SKiDL are helping you out!
As for panelizing, that’s an area I haven’t tried to automate. I just use the PCBNEW ‘add board’ feature to combine several PCBs. I have a mousebite component that I place around each board outline when I create them. The component has two versions of footprints, one being a mousebite with several drills and the other just being a straight piece of PCB edge. Then I just change the footprint at each location where a mousebite is or is not needed.
I’ll bump this thread with a bug report I submitted, you could make use of when they fix it.
In present PcbNew, you cannot load Lib-value, via netlist.
You can create a netlist with no value line, and NET-in with no errors, but that blanks the part value.
ie it has fetched the Library part fine, and then replaced the Lib-value field you carefully put there, with blank. Almost works, just one bad decision.
When that is fixed, NET flows will be able to be optionally more BOM based, and use libraries of part-coded items.
Example -
Digikey part number order code RMCF0805FG1K00-ND
That’s RES 1K OHM 1% 1/8W 0805
I’ve also created a script that Exports a KiCad NETLIST from pcbnew, which can be useful as a verification check.
That’s also useful where import-Non-KiCad Board file was used - in this path, there may be no reference NET file.
Could be an interesting tool to create parametric design such filter (e.g. creating a GUI to select butterwork, bessel, bandwidth, …) and etc…