Now I understand where the confusion started. My intention was to route both bus wires around the left S1 pad as a differential pair. Not split the pair into two separate wires.
In your final solution it also looks good, except from the TVS diodes which still have stubs. Also, the left TVS diode has a long track before it connects to the GND net, and this is also not good. Hazards such as ESD discharges have steep flanks and high frequency content, and this makes wiring important. The goal here is to shorten tracks, and even more important, minimize loop area.
I also noticed that in your first screenshot, pin B7 is a D+ and in your last screenshot this pin is a D-. After checking with Wikipedia, the D- appears to be correct. I assume you discovered this error in the schematic, changed it and updated the PCB. This does update the nets and the pad names, but KiCad does not change or delete copper tracks by itself, and that is likely how the confusion got started.
At picture in your first post you have D- connected to A6,B6, and D+ do A7,B7.
Now you have D- connected to A7,B7.
What is the reason of such change?
I remembered that in my design I had a solution like you have now, but looking at your picture from first post and seeing it is not possible there I supposed that you have D- and D+ in reverse order at your IC. I couldn’t check it being at home. Now I see that you have it in the same order then me.
You should ask yourself how it happened that you have it connected as in your first picture (and when you connected D+ with D-) as something that allowed you to do this is potential source of bugs.
I prefer to not have smaller clearances then needed. I see you have probably 0.1mm clearance between A1 (GND) pin and +5 Via. Isn’t it too close to each other?
At the same time you have very big clearance at zone.
I typically use 0.2mm between tracks and 0.25mm for zones.
Because of these two positioning holes for this socked I had to define smaller than usual clearance between copper and hole.
KiCad is not the program saying ‘I always know better then you what you want’ and user (if he wants) can do something against rules. When in Interactive Router Setting you select ‘Highlight collisions’ mode you can route against rules. Running DRC will find all violations you have done working that way.
I have never used ‘Highlight collisions’.
I think I fixed everything now. I just made the move from EasyEDA to KiCAD and I think that’s some of the source of my issues. This is also my first USB project. Lots of good tips guys. Thanks
improving clearance between VBUS vias and the USB connector pads no need ot be at minimum clearance) , you might just reduce the via size if you dont want to move them. The heavy traces off the connector pins may reduce yield. (heatsink)
-and increasing distance between diode SMT pads and the ground ( D1, D2, D3 vias are all too close- you wont get better perf being so close, just reduced yield) … . (C5 Vcc via is OK) so they dont suck solder or cause heat sinks during reflow…
also suggest on your USB chip, the Vcc pins 6 and 7, bring them out off the chip radially, otherwise it becomes difficult for the fabricator to know if that’s a short or not after reflow. the copper even masked may assist a solder bridge.
looks like you need to adjust the rules on your diff pair they current show a violation at the USB chip to adjacent pins (clearance )
check if vias are permitted under the USB connector. ensure tented.
I’d be surprised if you need that many ground vias under the USB chip. probably one or two are enough. That probably depends on the copper thickness and hence via path (electrical and thermal) .
I would suggest against using silkscreen around / near fine pitch SMT pads as it may lift the stencil. very much vendor dependent with silk screen thickness / process.
In past I didn’t know about it and for many years placed vias like this (or even closer) and never heard a word form contract manufacturer about it being wrong. As I always have no room at PCB I still do it that way sometimes.
Agree with it but I was also connecting neighboring pads that way and noticed no problem until I did it with 0.4mm raster IC without solder mask between pads. Now I don’t connect such pads directly.
Not sure, but I suppose that distance between pads is 0.2mm and clearance is 0.2mm. I dislike more the 0.1mm clearance for other nets. It is what I have written:
From the looks of it, you fixed the most important issues. For the rest, there is always a nearly infinite amount of little details you can keep on tweaking.
To me it looks like the tracks on DTR, Net-(U2-VBUS) and NET-(J1(CC2) have very thin copper tracks. Are these compatible with your PCB manufacturer? In general, when you use the thinnest tracks you find on the website of manufacturers, you already have one foot in the “danger zone”. Most people keep tracks 20% or 30% wider. The via’s on these tracks are also quite small, and the same rule applies here. Small via’s often also cost extra, because manufacturing becomes more difficult (slower drilling, risk of breaking etc).
And another thing…
A few posts back I advised to remove the stubs on the TVS diodes, and that looks good now. There is also a (small) issue with copper balancing. For 2 pad SMT parts, when one pad has much more copper then the other, heating will be a bit uneven during soldering, and this increases the risk for “tombstoning”. This does not matter much for DIY or small production runs, but when production runs get bigger, every small thing that has a potential to reduce yield or requires rework starts adding up.
I also see an overlap between the clearance of the NPTH hole on the USB connector and the GND pad.
Have you ran DRC? Does what other errors does it give you?
I suppose USB-C connector connects cable wires to A pins or B pins depending on plug orientation (not sure of it, but I think it is very possible).
But you have equal length between IC and B7,A6 and between IC and A7,B6.
If I’m right with connecting to A or to B only then however the plug is inserted you don’t have equal track lengths. Is it what was your goal?
Yes. USB-C connectors are designed symmetrical. They can be rotated 180 degrees.
This is true, but not an issue. The D+ / D- pair is only used for USB2, up to “high speed” (480Mbit/s). If I assume a signal propagation speed of 70% of light speed, then I get a bit length of:
0.7*299e9/480e6 = 436 [mm]
The few extra millimeters are not going to be important in this case.
That I know. But theoretically it is possible that plug has both A and B contacts and cross-connected inside. I don’t think they are but It is why I have written that I’m not sure if only one side (A or B) is connected.
I know, but OP during whole thread was trying to make tracks equal length. If he will connect D+ from IC to B6 first he will be closer to ideal.
Are you sure the other side of the route pins are correct? I suppose you are using CP2102 and the first entry you wrote is about changing orientation of the D+ D-. So, I have the same problem
For my layout, I am using USBLC6 from ST as ESS Diode, but we have to somehow change the orientation. I don’t like the idea of routing over S1 and having via under connector. So, for my scenario the best way seems having a via after ESD.
But, for my board. I think it is going to work anyhow. It is too slow and routes are too short.
Welcome on the forum.
You answered to my post so I got notification that someone did it.
I will not read the whole 2 month old thread to remind the problem and its solution.
But it was certainly not me who was using something the discussion was about.
