This is question about powerflag
I’m wondering that I need powerflags for all Power source and Grounds?
For example
I use power source such as 3.3V, 5V, 12V
and two Grounds (analog and digital)
So totally I have 3 power lines and 2 Gnd lines
then I need to add 5 Power_flag for each of them??
or Just use it for one Power source and Gnd to avoid ERC error??
Please let me know
I’m not English user so hard to understand all of User Guide’s contents.
Here’s below Sreenshot of User Guide (eeschema.pdf)
The way power flags are used in your screenshot makes them basically useless (That way they are just “ERC please shut up about power supply warnings”)
If you however place them as near as possible to the source of power for your board then you will get a check if everything gets power that needs it. (Meaning place it at the connector that supplies your board and after every passive component that is placed in series to that.)
Another alternative way would be to give the connector pins that supply your board the type “power output” (Meaning a custom symbol)
This however breaks down if you have passive components in series as it does not really make sense to do the same for these.
That is not what i wrote! I told you the way you show it to be used is useless. I gave you an explanation on how to use it such that it makes sense. And part of that is explained with the sentence you do not understand.
For more detail: I gave an alternative way that does not rely on power flags at all. (Some people simply prefer it that way) For this one creates custom symbols for every component involved in the supply chain. (These custom symbols then have the pins involved in the supply chain set to power output where necessary)
The sentence you quote is there because it is not really sensible to make a special fuse or resistor component with one pin set to power output. (What happens for example if you copy that resistor symbol and place it where no power supply line is? This could again be something that hides a true error or it could if you are lucky generate a false positive ERC error.)
Because of these downsides i feel that it makes more sense to use the power flag for such cases. (And by extension maybe even for things like connectors if you are not prepared to fully redesign the graphics of it to clearly communicate that power comes via this connector.)
If you do not care for an additional check against the common mistake of forgetting to supply components then use the power flag as shown in your picture. Simply place it where ERC complains and be happy that it stops complaining. This will however not help with finding true errors in your schematic as it simply hides the symptoms of it. (Like taking a painkiller for a broken leg without fixing the leg itself. Yes there is no pain anymore but the leg is still broken.)
Power_flag just says to KiCad: “Even if you don’t see it, this net has power source connected to it so don’t cry that nothing powers that net.”
From that unswer yourself your questions.
Rene don’t likes my approach but I always run DRC for PCB and never run ERC for schematic (I don’t mark unconnected pins as unconnected, don’t use Power_flags). For me such schematic looks clear.
I didn’t tried it but as I understand what Rene said if you use in power line any passive element then KiCad losts the information that “Some source of power is here” and you have to put next Power_flag just to say that after that passive element the power is also present. I power each IC by multilayer ferryte bead so I would probably need to add Power-flag for each IC at my schematic. And for ICs with separated power for analog and digital part two Power-flags would be needed. I would hate such full of Power_flags schematic.
If you are sure of what you are doing you can consider my approach.
I find the unconnected pins crosses one of the most usefull parts of the ERC check.
They guide me to think about whether it’s safe to leave some pins unconnected and sometimes they uncover omitted or misplaced wires.
It is possible to omit ERC, just as it is possible to draw a PCB without a netlist but the tools help to reduce human error.
Most of the PWR_FLAG’s I place are very near the power input connector, and I find them usefull to ensure proper power connections to all IC’s. I woul even welcome different PWR_FLAG like nodes for different voltages, especially when working with mixed 5V and 3V3 logic.
An easy way around placing the PWR_FLAG’s is to define the pins of the power connector as power output.
If you do not want to use the power connection checking, but do want to use the rest of the ERC checks, then you can simply edit the ERC options to green for the power input / output pins.
I am not sure if the error message for not driven power input even appears in that matrix. This check might be similar to the check for not connected rule which does not appear in that list either.
Well, this makes me think of a possible experiment to try, combining the power flag function (of providing a power output type pin) with the power symbol function (of providing a global power label). Copy a power symbol (for example +5V) to a new symbol with the name <voltage>_Source (so the example would be +5V_Source). On this new source power symbol change the hidden pin type from Power input to Power output, but keep the hidden pin name the same (for the example +5V). Then replace the relevant power symbol closest to the in-circuit source of power with your new custom power flag symbol. Make sure there are no regular PWR_FLAG symbols on the net and run ERC then highlight the power net to see if this new symbol works as intended.
This won’t necessarily resolve @Piotr’s use case of putting a ferrite bead between the power net and an IC’s power pins. For his use-case it might be better for him to simply change his IC’s power pins to non power type pins to hide the issues, or have a special ferrite bead symbol that has a pre-determined pin as ‘Power output’. Unless he also connects the GND pins to the GND net through passive components (like a ferrite bead), this might be a solution for him on the GND (or multiple GND) nets…
GND pins of ICs I connect directly to PCB GND, but sometimes at power input to PCB I put ferrite beads on both +12V and GND lines.
About 14 years ago I took PCB design (with Protel) from someone else and to tell you the truth I just didn’t know there is something like ERC. As I never needed it I didn’t serched for it.
combining the flag and the label will not work as you only want to mark one place where power comes in but will want to have many places that receive said power.
What i would like is some way of defining for ic power inputs which supply range they accept and some smart way of telling kicad which supply line is at which voltage.
Or maybe even a valid voltage range for every pin and a expected output voltage range for output pins.
Sadly i have not yet a full plan on how i would like this to work exactly
My thought was (again using +5V as an example), the +5V_Source symbol with the hidden power output pin named +5V would only be used one place, ideally where both you and I suggest using the PWR_FLAG symbol. Everywhere else the regular +5V symbol would be used. What would show on the schematic is the symbol name (+5V_Source vs +5V) so it would be obvious if the source symbol would be used multiple times. If the designer does accidentally use the source symbol more than once ERC will flag one of them, telling them to fix it.
I don’t know if I’ll have a chance to experiment with this in the near future, but I thought I would throw the idea out before I forgot it.
I think the use of multiple symbols breaks down for such a usecase. Something similar to the not connected on purpose marker might however offer a more flexible solution (That tool could then have a property for the voltage level for example)
It is true that my suggestion would basically double the number of power symbols instead of only having one extra symbol as it is now. But it might be more intuitive to the new KiCad user (or the non-KiCad user reading a schematic generated in KiCad) than the inscrutable PWR_FLAG symbol. Honestly, my intent isn’t to give the librarians more work. You and your team have done an incredible job tackling the Sisyphean task of library management, all in your spare time.
While, yes, something similar to the not connected marker might be more flexible, that doesn’t exist (yet). So my idea is how to handle the ErrType(3): Pin connected to some others pins but no pin to drive it a little more elegantly with the tools that we currently have. How does something called “FLAG” drive anything… Having a power source type symbol that links to regular power symbols conceptually makes sense to drive other pins.
But this is all academic unless someone is able to prove that this idea does or doesn’t work with the existing KiCad stable release. As I mentioned above, I don’t think I have time to experiment with it. But if anyone else wants to take up that mantle…
Though, of course, the counter argument is it may not be intuitive to someone who doesn’t know how KiCad does things that a power symbol called +5V_Source is on the same net as +5V and might think that they are two separate power nets… More thought is required…
There is no getting around the fact that some item must be the source. KiCad, now with V5 has a separate field in the symbol library called “Symbol Name”.
If it becomes allowed that power symbols were to also be tied to a net, then all that is needed is for the duplicate Pwr Symbol to have it’s pin as Power Output.
The text does not have to be different when the symbols are placed, and a menu toggle similar to Show Hidden Pins could show the Pwr Symbols pin description.
There is going to be some ambiguity no matter the solution, and this does not seem to me like a bad solution. And, I think for some, 5V_Output and 5V_Input makes sense in a basic logical way.
I read threads on this forum to learn about KiCad since I am a very new user and know very little about electronic circuit design so I know I am not an expert by any stretch of the imagination. I have only posted a few times so I don’t want to step on any toes here but I think it needs to be pointed out that the screenshot in the first post of this thread is not a circuit created by the original poster. It comes from section 6.5.4. Power ports connection in the Eeschema Reference manual.
Since the very first response states that “The way power flags are used in your screenshot makes them basically useless…” then isn’t the first thing that needs to be done is to correct the documentation?
The way hidden pins work electrically is they connect to the net that shares the same name as the pin name. That’s why the existing power symbols use them. So having the pin names different between the two symbols won’t work. (The PWR_FLAG symbol works on any net because it doesn’t use a hidden pin trying to automatically connect to a net name.)
I’m not sure what you are getting at. KiCad symbol libraries have always had a field called “Symbol Name”. That is how you choose which symbol to use out of a library. And because of this, symbol names within a library must be unique. (And I just checked, the value field and symbol name field are linked together in the symbol editor in v5.1.) My first thought was to have two symbols with different shapes with the same name. My second thought was that wouldn’t work unless they were in separate libraries and I didn’t even want to consider suggesting that. Doubling the number of symbols in a library is bad enough, suggesting two separate libraries with one just a modification of the other is worse logistically.
And again, we get to the point that I’m trying to think of a work flow that works within the existing tool set. Not a program feature wish list item.
Edit: Oops, quoted the wrong paragraph first. Corrected.
Just tried that method again, and it did not seem to work. I don’t have time, at the moment, to work out what I probably did wrong.
There has to be either, PwrFLags, Custom Symbols, or specialized Power Ports that are allowed to act as Power Output. I like idea of the specialized Power Ports because it would eliminate the weird PwrFlags from the schematic and still comply with the ERC.
I am fine with any, and all, suggestions to get rid of the PwrFlag on printed schematics.
