Hi Martinn,
just out of curiosity… what upper speed limit (clock speed) do you expect for this implementation of the ALU ?
More likely, a digital oscilloscope and a logic analyzer. I’ve found those to be a good combination in my project recreating a the i4004 CPU using discrete components.
Had this discussion taken place in 2012 rather than 2022 I would have been very interested. I wrote a Java program to trace the bitmap schematic produced by the 4004 Anniversary Project team and generate 40,189 lines of Eagle script to recreate the schematic.
However, 10 years ago (omg, I’ve been working on this for 10 years!) KiCad was not a viable alternative to Eagle. These days I’d want to write the program in Python to generate the schematic for KiCad. Unfortunately, I believe the stable Python interface to Eeschema won’t come out until KiCad v7, so it’d have to generate the schematic file directly.
Have not built it yet… I simulated the carry chain of an 8 bit adder with around 1 us delay. So ALU tpd is probably in the low us range. The two phase FF is easily running at 1.5 MHz, but the combinatorial logic will be slower.
Definitely I am a few decades late. However, what this really makes it possible is the JLCPCB SMT assembly. Although (a few) people built room-spanning installations with THT transistors, for me a manual assembly of a several thousand component PCB (SOT-723!) is out of the question. Autoplace and autoroute are an added bonus.
I had this idea of trying out a gridless placement optimizer.
The idea is to read out nets and courtyard dimensions of the components from the PCB file and find a placement with minimum total net length.
The algorithm moves components by a random amount and tolerates increasing net length according to a decreasing “temperature” value shown in the title of the graph (this is the core concept of the simulated annealing optimizer).
Not sure if this will ever be of any use, but it definitely is fun to watch!
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