At schematic C9 is at VBUS and C10 at 3V3 but at PCB it looks different.
Placing all 100n capacitors together has no sense.
If your IC have only 2 VCC supply pins than you probably need only 2 100n capacitors.
It looks that you have GND at bottom but you don’t use it to make your connections.
You can look at one my PCB to compare:
All vias you see there are GND. Compare their number with your 2 GND vias.
And my bottom (blue) GND is continuous - not broken by any tracks. Continuous GND plane gives minimal possible impedance for return current for all signals.
You have 2 tracks USB connection. But in USB signal there are also intentional common mode signals and they need return path (from uC to socked GND pin) but just there you have big break in GND zone. Imagine return signal instead of taking the shortest way have to go around that break.
I’ve always likened this sort of schematic to an unassembled jigsaw puzzle. It is a lot of trouble for a person not familiar with the work to understand the drawing. And a regulator in a box labeled USB?
I’d suggest removing the blue boxes and attaching the switches, clock, power supply and socket directly to the processor.
Inputs to the left, outputs to the right, power from above and Gnd all pointing down. A bit like most flow charts and book pages.
If all the symbols are connected together with wires, it is much easier to read and notice design faults.
The crystal layout can be tricky – you want a tight cluster of components and short traces. Let me offer a couple of layouts I use for the stm32 oscillator. These are using 4-pin xtals in a 3.2x2.5mm package, 0402 npo 22pF caps, and an 0402 or 0603 series resistor on osc out (I use 22 to 100 ohm just to throttle the osc gain a bit). I wrap ground trace stubs around the sides to isolate the xtal a bit from surrounding top-side stuff. A solid ground plane below.
Shortly (month or two) I will be designing my first PCB with STM32. In their AN2867 they suggest to not only make GND guard ring on top, but also to cut GND plane under oscillator from the rest of GND plane (see Figure 14 in AN2867).
The idea is to not allow other currents than oscillator ones to travel under crystal connections, but I wonder if such cut will not make crystal frequency emissions from PCB higher, and as my devices are in plastic case…
Have you considered such cut and decided to not use it or you have never even considered it?
If I were using 4 layers I would probably make such cut at nearest GND plane under crystal and have second GND plane without it. Just my imagination tells me it would be good compromise.
Thank you all for the quick replies. I’ll try to work through this methodically.
I copied this PCB and schematic over from a larger project I’m working on. I didn’t realize that the symbol identifiers wouldn’t carry over. I’ll try to redo the layout of the PCB with the re-annotated schematic.
Ok. I wasn’t sure about this since the video recommended one per VCC, but the schematic I was basing my design off of used four.
Thanks for the advice. I’ve reworked my crystal layout with a ground plane cut.
I’m planning on using nearly all the I/O pins. Is there harm in putting a via to an inner plane directly onto the pad, since some I/O’s are blocked by other traces (particularly on the left)? This will be machine assembled.
You didn’t understood what was said and the example at the picture in the AppNote I mentioned.
The GND at bottom should be:
continuous at whole PCB, as you had it before, or
filled plane under crystal isolated around except having connection to the rest of GND plane just under the crystal tracks going to uC.
I don’t know which solution is better. I asked hopping to hear @teletypeguy opinion.
U2 should have pin 1 down (you can not only rotate symbols but also mirror them). Then GND symbol will naturally be pointing down.
SW1 should be on the left or left down, R2 toward up, and wire goint from it to uC frist going to the right.
Here is schematic of one of my devices.
Even details not visible you should get general conceptions.
You understood.
From computer (KiCad) point of view it is not important but for human how you had in your previous version your supply drawn was very … untypical.
Yeah, I dunno. I have read several papers on this and never tried a ground moat below the xtal parts. To do it properly It would need a single center via to connect to the main ground plane system and the top caps and xtal gnds would need to tie to that via – kind of a pain to lay out.
I have always wanted to make a proto with two identical layouts – a solid ground plane on one layout and a moat layout on another, and compare the two. Some years ago I was chasing down a spur that exceeded compliance prescan testing. While you can’t reproduce a screened test room in your lab, there are options for testing relative changes to your circuit. I made a TEM cell (had a sheet metal place up the road cut and bend the sheets) which is great for relative testing between changes:
The stm xtal is only 8MHz and the signal is mostly sine (minimal harmonics). When I have taken products to the emi test lab the spurs are more dominant at the pll freq the cpu is running on (eg: 72 MHz for an stm303 was a high spur but 8Mhz was not a problem (they don’t even look below 30 meg iirc).
I think the series resistor on the osc out is more important – it can be adjusted to lower the oscillator gain (try different values from 0 to 1k or so and look at osc out signal). I typically use 22 to 100 ohm.
I have also didn’t tried it ever but it looks that ST thinks (or at least one AN writing engineer thinks) that it is really important.
Are you sure it is because of pll and not just 8MHz odd harmonics. I had 8 bit uC without pll and got dominant lines around 80…90 MHz (don’t remember if crystal was 8 or 12MHz).
Measuring method that specifies 1m cables makes emissions being most effective when 1m is quarter wave antenna.
I will think about it. There are probably different internal generators in one and other STM32 uC. I don’t remember what exact STM32 part we will use (it was low power serie, I think) but when I break the work on it I was sure to connect crystal without any resistor.
If remember well in other uC you could set generator to work with high power or low power.
I remember reading somewhere that you can find R breaking oscillations and then use R/3 (or R/2 - don’t remember).
Perhaps. But the xtal signal is mostly sine, so harmonics would be generated by the internal pll circuitry. Unsure how changing the xtal layout would affect that.
I am no emi expert, but I have been through the compliance process more than once, and have thousands of products produced running stm32f303, f051/71/72, and some f4 stuff, all having the series resistor. The emi part was one factor – we also did ce approval on one product which added susceptibility testing with the sparky-sparky gun, and the most brutal test was when they enclosed the usb cable in a long metal sleeve and they poked many-kilovolt transients into the sleeve. The product needs to keep running (or reboot gracefully). While the stm watchdog restarted the device, the software at the pc end had to be changed to detect the device reset and restart data streaming. It was interesting at the time, but I hope to never deal with ce again.
I agree.
I think that in uC without pll main sources of harmonics are all internal registers switching at xtal frequency. But I suspect xtal layout because it is much bigger than what is inside and even through crystal mostly sinus goes I’m not sure of generator output signal (voltage or current) shape.
I would move GND via near pin 4 to the right to make OSC_IN shorter.
I would connect top GND track to uC GND pin.
I would finish down GND track with via to GND as close to Reset track as possible.
I have in all my footprints Courtyard such defined that I then position elements with just touching their courtyard lines (I’m speaking about C1 na C3 and Y1).
I would shift all crystal circuitry ac close to uC as possible to make all these connections as short as possible.
Connecting C3 to GND track going from crystal pin 2 will allow to route OSC_IN under crystal making it shorter.
Better, but you can still scoot it down and to the right a bit. And you can extend the ground stubs a bit more. Then, when you add a top ground plane (you should, and it is easy) it will snuggle up to the stubs. You already have a bottom ground plane – it is easy to add the top: select your bottom plane, press E, and add a checkbox to the top layer (and inner if applicable and desired). Tweak the clearance to your liking, thermals… You can remove islands (and should if they will be floating) or allow them and add some gnd stictching vias to connect them to the main plane:
I have no idea what Bigtechtree is using for a crystal (and just because you find some circuit online, does not mean it is optimum or correct), but typical 8MHz xtals are about 20pF parallel mode so 10pF caps are kinda small. I am currently using these xtals:
Mouser 520-80-20-33-JEN-TR3 – Crystal, 3.2x2.5mm, 8.000MHz, 20pF, 20/50ppm, 400-ohm
JLC/LCSC C648987 – Crystal, 3.2x2.5mm, 8.000MHz, 20pF, 20ppm, 200-ohm
The resistor is optional. I always include it but it will work without it.
The ground plane can be as simple as a big sloppy trapezoidal polygon that is outside the edge-cuts – you set copper-to-edge clearance to something like 0.5mm and it fills properly. I usually draw the polygon on the bottom layer, then select it, press E (properties) and add the check box on top and inners. Then it fills nicely on all layers. Here is a little board (I drew a fancy polygon for a bit more control, but the sloppy polygon also works). Unfill the zones (Ctrl-B) and peek at bottom only:
For my PCB, I’ll need to use nearly all the available I/O pins. Is a layout like this acceptable, or should I switch to a 4-layer PCB? This routing doesn’t cut my back ground plane.
