Problem with hidden pins

I don’t know, I found this schematic to connect the unused units so I did it.
I’m also curious what’s the difference to use one unit instead of three chained to generate frequency given a variable capacitance like a soil moisture probe. Googling I found both schematics but I don’t understand the differences.

Either way will suffice, the important thing is to not leave the inputs floating. Usually you would connect all unused inputs to ground, the only reason to daisy chain them would be if it somehow made the layout easier. Daisy chaining them will cause a slight increase to the current used by the device so you might want to ground the inputs for a battery powered circuit.

It depends on the oscillator topology used. Any inverting logic element can be used to make an oscillator since they inherently provide a 180 degree phase shift. An oscillator is often made from one, two or even three such elements and sometimes another gate is used to buffer the output of the oscillator. In fact, any number of elements could be used to create an oscillator but there is seldom any need to use more than three. An odd number of elements will inherently oscillate where as an even number need to be forced into oscillation usually with enough capacitance to add additional phase shift. Single element oscillators need special care as the feedback resistor will make the element operate in a linear mode and it may or may not oscillate. If it does oscillate it may not be stable. However, the use of a schmitt trigger element prevents this making it a reliable oscillator but it does become sensitive to supply voltage variations as the schmitt trigger thresholds vary with supply voltage.

That was a little more long-winded than I intended but hope it helps.

I found this, it might provide a little more information:
CMOS Oscillators

Thank you again.
Very useful document. Since I have a stabilized Vcc and a soil moisture probe doesn’t recquire a precise frequency, a single unit will suffice.

Daisy chaining was used because on many inverter packages it involved linking adjacent pins, simplifying the tracking.
On a ground plane board it offers more chance for a cut and strap modification to extract a “spare” inverter.
I don’t see why it would consume more power with CMOS logic

How I handle this for grounding inputs is to mask the input pins with a fill keepout zone in the ground plane and then on an external layer without the ground plane I run a trace to a via. That gives a trace to cut on the finished board to mod the unused gate. (I usually do this as one of my last steps because it can be quite annoying to remember to move the fill-keepouts if I decide for clearances or routing reasons to move the chip…) YMMV