Here is a good video describing what I’m saying.
I think vias might be more effective.
Even though I don’t want to solder SMD’s, this is a good reason to use them to reduce the number of oaths between layers
I have some mixed feelings about that video.
In some ways it’s really good to show the effects of the reference changing from one GND plane to another, but there are too many things missing in the simulation.
First, there is no connection between the two GND planes at all, which makes me wonder what is actually being simulated.
Then from about 2 minutes on I got bored and I skipped to 11 minutes, where the stitching via’s are added. This has a huge effect (as I expected). But they talk for minutes about the differences between 4 via’s or only one, and they don’t show a simulation of what it looks like with only one or two via’s, and the effect of changing the distance between the via in the track and the stitching via(s).
But it does show some definite results, and for that it’s good.
C8 is a smoothing capacitor, as is C9.
You need a pair of 100nF (=0.1uF) V+ to VB, and V- to VB. If you want to go mad, put a third from V+ to V-. These are “decoupling” capacitors, filter any high frequencies on the power rails, often make the op amp a lot more stable.
Without thinking, I always add decoupling caps to both rails for op-amps, and to the 5v for logic. They should be as close to the chip as possible. If you have a load of chips, you can probably share the caps between 2 adjacent chips!
Here’s a bit of one of my boards:
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Thanks, I’m tracking you now. Picture was very helpful. BTW, I also found a video of Bogatin talking about best practices for 2 layer. He stated the same about decoupling caps and much more. I was actually doing a bunch of these, but really didn’t know why. I need to do more research on return paths and what is best for PCB layout.
Thanks again for all the help. Really useful to make me think through the process.