I don’t like guessing. If you post your project, or even better: a simple dummy project with a similar setup and that shows your “connector problem”, then we don’t have to guess anymore and give more fitting advise.
Edit: also note that Piotr (see below) is now the 4th person who does not understand it and is guessing.
I just can’t understand your problem.
I’m using pin headers at PCB with no problems. May be the difference is between using and implementing.
When I want to have pin header at PCB I just use the pin header symbol at schematic that has associated with it pin header footprint.
Thanks for the inputs,
I understand now. I think my problem was a terminology issue. I was looking for headers in the schematic editor, but I found connectors and was struggling to figure out how they were implemented for male and female headers. I eventually deciphered the terminology.
In the footprints they are called pin headers. I guess the reason is that the connectors symbols in the schematic editor can be used for multiple types of connections and are more generic.
I initially just added the pin header footprints to the PCB and forced it to work. I am pretty certain that what I had was accurate and would’ve worked, even with the DRC errors I was getting.
I have gone back and changed the schematic. I haven’t finished, but based on what i have so far, it should clear up all the errors.
Yes, just like how many different BJT transistor types and packages fit the six different symbols?
It’s an interesting spectrum when you think about it. Device symbols for example, could in theory be all N-pin boxes. But we have special symbols for op-amps, muxers, etc. Digital gate symbols could also be boxes, like the horrible IEEE symbols, but we have different shapes for AND, OR and XOR, plus the negation circle. So it’s not wrong to look for a more specific symbol first and then fall back to a generic symbol. Some specialised connectors could benefit from their own distinct symbols.
But there are people who take it to the extreme and want DIP IC symbols to look like DIP packages right down to the sequential pins. This actually a throwback to an earlier age of schematics, like this one:
Thanks
I’m fairly new to kicad, but have good sense for design as I’m a retired aero engineer. I can get a clean schematic fairly easily, but when I get to the pcb stage and I’m trying fit the physical dimensions of a box, things start to break down.
The naming conventions for footprints are matched because you have a physical device.
Naming conventions in the schematic symbol generator often throw me. I understand why they’re that way, but that doesn’t mean I can find them easily because I don’t always know the jargon.
Thanks to everyone, as it pushed me in the right direction. I will post my schematic when I get to my computer.
I started to use KiCad in 2017 (V 4.0.7). First what I have done (before designing first PCB) was to make my own libraries and I use only them. All symbols I make myself. All symbols have footprint attached and I never touch it after used at schematic.
When I am using an element with footprint I have never used I copy (using file manager) some footprints from KiCad libraries (I don’t see them, I do it just based on their names) into my library and there I select the best of them (deleting all others) and then modify it according to my standard.
When I am trying sometimes to report a bug with example project I switch into KiCad libraries to do that. I am totally lost then.
In my opinion having your own libraries even needs some work at the beginning helps you a lot later.
I have described my KiCad file structure here:
Good advice, I am on similar path. I have been making my own symbols and footprints. I have been using both. I find many of the symbols too big for the symbol editor for my taste. It makes sense to import them into my own libraries. I currently let mine sit with the others. I haven’t noticed any problems but I can see where an update might smoke my symbols and footprints.
Agree.
Major upgrades (eg.7 to 8) require you to reload your personal libraries. There is some very useful information on library manipulation in these (here and here) FAQs.
Saving individual Kicad library symbols and footprints to personal libraries is as easy as:
Open the appropriate Editor, find the appropriate part then Right Mouse click > Save symbol/footprint/3D as > Rename if required > Highlight the receiving library > OK. Even scrolling can be minimised with the prudent use of nickname changing or “pinning” libraries.
Kicad is designed around creating personal libraries. One of the first changes I made when starting to use this programme was to rearrange the Device library into several, more workable, personal libraries. 
Quite the opposite. An update will leave your personal libraries alone, but very often change the standard libraries.
Just make sure that your personal libraries are not in a system location, but a location that gets backed up regularly.
Some simple feedback, based on having designed several small audio boards myself:
Thanks Paul. It helps greatly, It has spurred me to a large amount of research on design guidelines,
What extra filtering are you speaking about?
I assume, decoupling cap . . . there already though, C8 ?
Here is a good video describing what I’m saying.
I think vias might be more effective.
Even though I don’t want to solder SMD’s, this is a good reason to use them to reduce the number of oaths between layers
I have some mixed feelings about that video.
In some ways it’s really good to show the effects of the reference changing from one GND plane to another, but there are too many things missing in the simulation.
First, there is no connection between the two GND planes at all, which makes me wonder what is actually being simulated.
Then from about 2 minutes on I got bored and I skipped to 11 minutes, where the stitching via’s are added. This has a huge effect (as I expected). But they talk for minutes about the differences between 4 via’s or only one, and they don’t show a simulation of what it looks like with only one or two via’s, and the effect of changing the distance between the via in the track and the stitching via(s).
But it does show some definite results, and for that it’s good.
C8 is a smoothing capacitor, as is C9.
You need a pair of 100nF (=0.1uF) V+ to VB, and V- to VB. If you want to go mad, put a third from V+ to V-. These are “decoupling” capacitors, filter any high frequencies on the power rails, often make the op amp a lot more stable.
Without thinking, I always add decoupling caps to both rails for op-amps, and to the 5v for logic. They should be as close to the chip as possible. If you have a load of chips, you can probably share the caps between 2 adjacent chips!
Here’s a bit of one of my boards:
Thanks, I’m tracking you now. Picture was very helpful. BTW, I also found a video of Bogatin talking about best practices for 2 layer. He stated the same about decoupling caps and much more. I was actually doing a bunch of these, but really didn’t know why. I need to do more research on return paths and what is best for PCB layout.
Thanks again for all the help. Really useful to make me think through the process.
