I received this feedback from my PCB production house. “the ratio of copper pour on both top and bottom trace layer are less than 30%, and clearance bettwen traces are less than 0.127mm, it’s out of our production capability as it has high risk of short circuit during production.” I understand the 0.127mm cleance, however I am not sure about the 30% issue. Is there a design rule check in KiCad I can turn on to test for this issue?
I don’t know for a fact but I think not . . . a “Maker” I follow on YouTube had to go through the same thing recently when JLCPBC changed their specs, all of a sudden boards they had made for him previously were no longer to their spec.
He ended up doing some significant layout mods using their new clearances on several of his boards.
Thanks @RaptorUK I have a lot of routing on the front layer to mate several 80 pin connectors. I can probably easily move half of them to the bottom layer and this might solve the issue.
just add a ground plane on the top and on the bottom layer. That will fill all the copper void.
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I suppose that when there are big difference in how many copper have to be etched at both sides than the process speed is different at both sides (even though the etching solution is stirred) resulting in to match etching at one side why at other there is still not etched what should be etched. The concentration of the etching agent varies between the two sides.
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Top/bottom copper aeras should be approximately equal or at least not significantly unequal. Reason being: copper - as everything else - shrinks and extends with temperature. So the board may warp if one side’s contraction is stronger.
Btw, for the same reason quality floor panels have a material on the backside that matches the thermal properties of the “good” side.
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