I’ve got a design ready to send for manufacturing and SMT assembly at JLCPCB. The design is too small for their SMT line, so I’d like to tile a bunch of them on a panel.
I’ve tried to use “append board” from a new project but it seems to do weird things to my filled zones. As I need a .pos file for assembly I don’t think I can use an external Gerber panelizer.
What’s the best way to make a panelized board and the files needed for SMT assembly from KiCad?
Have you tried asking them to do it for you? Might not cost as much as you fear.
What are “weird things”? I have successfully done this by using append board.
Currently there is no built in support in KiCad for making panels.
How can this be:
The “append board” option is not available when Pcbnew is used in a project, but it is only available in “standalone mode”, that is: directly opened from your OS, and not from KiCad’s project manager.
There are several tutorials and even scripts to work around and help with creating panels in KiCad. Here are two articles posted on Hackaday:
(And there are more & other helper scripts / tutorials on the 'net).
But when you start doing such things you always have to keep in mind that there is no real support for panels built into KiCad.
One of the things that go wrong is in situations like this:
I like to draw pentagons around my PCB, and then let the zones be clipped by Edge.Cuts. The irregular pentagon makes a Zone easy to select, and if something goes wrong in the Edge.Cuts layer, then you see it instantly when reviewing Gerber files before you send them off.
When you start panelizing such a board however, the whole concept breaks. You mess around with Edge.Cuts, (mousebites etc.) and the different zones with the same net are just merged into a single zone by KiCad. So you have to carefully manage the zone outlines yourself.
You also have multiple instances of each footprint with the same RefDes (“Reference” in KiCad speak) and this also complicates things. If you want to make some change to the PCB after you’ve made the panel, it mostly means you have to do the whole panel again, or delete the PCB’s from the panel and then integrate the modified version again in the panel.
(This spings an idea: Put your mousebites in the orignal PCB project, so they get copied & multiplied together with the rest of the PCB’s.)
JLCPCB even has a button on their site during ordering with something like “Panel by JLCPCB”.
My design isn’t large enough for JLC to allow me to panelize it using their system sadly. I also need control over where the mouse bites etc. are as some portions of the board are visible in the end product.
Any scripts I’ve found don’t seem to give me enough control over how everything fits together.
“Append board” almost works for me, but if I ever update filled zones the whole thing falls apart. I’ve tried doing it without updating filled zones, but then my mouse bites get plated which would short out the supply.
I also can’t seem to reliably append my board. Most times when I try the ratsnest goes crazy and shows a bunch of unconnected pins floating in the middle of nowhere:
I’ve guess you have now bumped into some of the reasons why I wrote earlier:
Panels can be done in KiCad, but automated functions fail because KiCad does not know what a panel is.
KiCad gets confused by the reatsnest, as there are suddenly several footprints with the same RefDes.
KiCad can’t separate the nets and zones from the different sections, and probably merges zones.
Because KiCad does not support this yet, you have to work around these (and maybe more) limitations yourself for the time being.
Sorry for not reading the whole thread, so it’s possible I missed some requirements, but I used GerberPanelizer from the GerberTools suite once before. It allows you to arrange the boards and add tabs with mousebites yourself.
As far as I’m aware GerberPanelizer doesn’t have any support for exporting a .pos file for the panelized boards.
Do you know if panelization support is coming any time soon or if it’s worth learning another tool instead?
I haven’t used placement data, so I don’t have any insights on this, other than what a quick search provided.
It seems the answer is no: https://github.com/ThisIsNotRocketScience/GerberTools/issues/100
But check out the links in the comments.
This issue has been open for two years, and has not seen much traffic in that time:
At the moment all development effort goes to bug fixing KiCad V5.99 and that will continue for some time (months, half a year, maybe a bit longer?)
If you hover over “V6.0.0-rc1” in gitlab, then it shows 2021-04-30, but I don’t know how realistic that is, and a release candidate is not a finshed product.
I have seen a number of features dropped for V6 and postponed to V7, while I have not seen panelization been put on the roadmap for V7 The search below currently lists 170 issues for KiCad V7, and apparently none is for panelization…
So my best guess is that it will probably be a few years before panelization support in KiCad will be added. Maybe more.
But such things are hard to predict. There is no hard roadmap in Open Source projects, and if someone (or a few people) volunteer to work on panelization (and coordinate with the other KiCad developers) it may be a lot sooner.
There is also always the possibility that a big sponsor comes along and wants to sponsor panelization for KiCad. In that case, contact:
I have had JLCPCB make panels of 15mm x 10mm boards.
With JLCPCB if you specify edge rails you can combine the width of these with increasing the number of boards on the panel until you reach the minimum size required. This does not affect the overall cost of the panel by much.
Do you know what was the exact reason why:
For example, quite often there is a limitation to the minimum width between V-grooves. Maybe you specified a too narrow gap for routing the board or something else such as indeed the edge rails that 636Steve mentioned.
I might have been wrong about the minimum size - I just tried to submit my board and they were happy to panelize it. Sadly they don’t seem to offer assembly on panelized boards so I’m back to fighting KiCad.
JLC: They would not assemble boards with V-groves. My boards were too small to assemble. One engineer told me to put a row of holes between the small boards and get them assembled as one then saw them apart when I get them. When I sent the files a different engineer told me they can not allow small boards (paneled).
So I made a large board that had 90 small boards on it. On board 1 the resistors are labeled R10,11,12… and board 2 is R20,21,22,… etc. I put 0.8mm NPT holes in the corners of each small board and separated them by 0.8mm. The price of one small board is not much lower than the price of a large board. The money saved payed for a low cost mill (cnc). I cut one large board apart and the mill idea works good. I use the 0.8mm holes to align the bit. For some reason they could not handle a large board with 90 "R1"s.
I tried a saw to cut the boards but the blades do not last.
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