But you’ve already mitigated that risk by putting it in version control, right @ChrisGammell?
On the subject of OSHPark PCB Rules… I had an odd thing happen yesterday. I had uploaded my gerbers and was getting ready to check out, when I was prompted with an “upgrade” option… swift service and higher tolerances. For swift service, I could have the boards delivered in one week (I think) for an extra $30… for the higher tolerances, I would have been able to submit a 2 layer board with 5mm traces and some smaller version of their via spec.
It seemed odd, because I’d never seen that as an option before that I can recall. Letting me know I could have used 5mm traces when I’m uploading gerbers seemed a little late in the process to tell me I did pay for the swifter service though.
Nope, those are new offerings, that’s why you didn’t see them before.
I wonder if they are doing some A/B testing, because I only see “Super Swift Service” for $89 extra, which I personally think is too much. $30 sounds more reasonable.
Could be. My thought was that it was based on board space availability, selling open spots on boards about to be shipped off at a premium over putting you in the queue. And yes, $89 is too rich for my blood, particularly if I’ve already got the expectation that it’s going to be two weeks. If I wanted it faster, I probably wouldn’t have gone to OSHPark in the first place.
I made a pretty simple KiCad template for OSH Park a while back, it might be a good start. I was planning to attach it, but it seems that isn’t allowed… Let me know if there is interest for it and I’ll upload it some other way.
Edit: I uploaded it to my blog: prjct.net/download/osh-park_2_layer_standard_order.zip
The upload is possible, you need to have a slightly higher “trust” level though. That will happen after a short amount of time. See here for more info: https://meta.discourse.org/t/what-do-user-trust-levels-do/4924
Close, but not quite. The minimum track width only has to take into account tolerances for printing the photolithography artwork and the process of etching. But annular rings have to also account for drilling tolerances (both drill location tolerance and drill diameter tolerance as well as the actual drill being slightly larger than the finished hole size in the design to allow for the thickness of the hole plating).
This is why OSHPark specifies annular ring separate from track width. Here are the specifications from their web page:
- 6 mil minimum trace width
- 6 mil minimum spacing
- at least 15 mil clearances from traces to the edge of the board
- 13 mil minimum drill size
- 7 mil minimum annular ring
The annular ring specification is how much to add to the radius of the drill hole so the math will be drill + 2 * annular ring. Thus 13mil + 2 * 7mil = 27mil.
That’s the value I use as well.
I think the key to this is actually calling this out in the KiCad interface vs using default annular ring (granted, this depends on how you use the Net Classes to start with). When I first made this mistake I put in a 13 mil drill and a 20 mil diameter. It looked too thin, which caused me to double check. Using the default values for drill/ring only shows the ring, not the drill inside it.
Quickly looking at the design rules and DRC dialog boxes, I don’t see anything to enforce a minimum annular ring. One would have to manually make sure that all pads are 2 * minimum annular ring (14mil with OHSPark) larger than the associated drill. Not only on vias, but also on all THT components. Might be something worth requesting as a feature addition to the development team.
KiCad has a Template option:
in the main Window there is a button ‘Start a new Project from a template’
(new Versions: ‘Create new Project from Template’)
if you click on this button you can choose from some templates -
on windows these are located in the main KiCad folder:
“c:\Program Files (x86)\KiCad\share\template”
(in the new Version: “c:*****\kicad-winbuilder-3.4\kicad\template” worked for me)
i have made a PCB-Pool Template according to there specifications.
you can download it at: http://s-light.github.io/template_PCBPool_20150105.zip
i posted this also at https://groups.yahoo.com/neo/groups/kicad-users/conversations/messages/19513
hope that helps
I downloaded a OshPark 2 Layer template Zip folder linked above and then opened the template in KiCad.
This provided the following design rules for KiCad:
This is the info I was initially looking for.
I figure that if somebody does not want to deal with downloading the template they can just copy the info from the image above.
If there is anything wrong with this info as far as OSHPark’s design rules just let me know.
Looks like what Oshpark says on their site, indeed.
It looks like 4 layer boards have different minimum track width and drill sizes.
The minimum specs for 2 layer orders are 6 mil traces with 6 mil spacing, and 13 mil drills with 7 mil annular rings.
The minimum specs for 4 layer orders are 5 mil traces with 5 mil spacing, and 10 mil drills with 4 mil annular rings.
I’ve always seen annular ring defined as such…
(remove the underscore b/w P & G in JPG. The forum won’t let me post images…)
which means that you would need to add two annular rings. However, I’ve made the mistake of submitting files with the via diameter rule set to one annular ring dimension and I got the board back fine. Use this knowledge at your own risk.
You can create different board templates and start a new project from that template. It’s not super convenient if you don’t know which board house you’re going to use when you start, but at least it’s something.
Same here. I’ve read (older) IPC specs and as I recall that is the correct definition of annular ring. But don’t think of it as adding “two annular rings”. Just recognize that the annular ring is an addition to the drill radius, not the diameter. So the mathematical effect that you describe is the same.
Often the annular ring is larger than the minumum track width because it needs to take into account drill tollerances (both in drill diameter and mis-registration) and the fact that if the specified drill size is the finished hole size the board house will have to drill with a slightly larger drill so the through hole plating reduces the diameter to the customer specified size.
QFT! The specified size is the finished size so over-drilling occurs to allow plating to shrink the hole size to the specified size.
This is pretty much what I did. I made a starter projects/templates kind of thing, then just put them in a special folder and made them read-only so I don’t accidentally hit “Save” and overwrite them. Seems to work fairly well.
For a more flexible method you can open your pcb file up in a text editor and replace the section of setup as required. You can copy out from existing projects and make a simple library. Not as good as being able to load in a suppliers validated rules file, but quicker than typing out every time.
As an example i’m using for OSH 2-layer is;
(setup (last_trace_width 0.1524) (user_trace_width 0.1524) (user_trace_width 0.254) (user_trace_width 0.3048) (user_trace_width 0.4064) (user_trace_width 0.6096) (user_trace_width 0.8128) (user_trace_width 1.27) (user_trace_width 1.778) (trace_clearance 0.1524) (zone_clearance 0.508) (zone_45_only no) (trace_min 0.1524) (segment_width 0.2) (edge_width 0.15) (via_size 0.6858) (via_drill 0.3302) (via_min_size 0.6858) (via_min_drill 0.3302) (user_via 0.8 0.5) (user_via 0.91 0.6) (user_via 1.05 0.7) (user_via 1.2 0.8) (user_via 1.35 0.9) (user_via 1.5 1) (user_via 1.8 1.2) (user_via 2.1 1.4) (uvia_size 0.762) (uvia_drill 0.508) (uvias_allowed no) (uvia_min_size 0.2) (uvia_min_drill 0.1)