Thanks for posting, very interesting!
I played with autoplacing a bit: Programmatically generating schematic
I used that for my discrete logic projects. You could have yosys generate a multiplier or and ALU out of transistors. No one would attempt to place or route this mess by hand. So I wrote an autoplacer, using the simulated annealing optimizer as it is done with FPGAs. This is easy for cell-based layouts (you have a fixed grid and just swap cells), more difficult for a gridless variable size optimizer (see my last post).
I then used freerouting as router, which seemed to work well enough. I did not continue with that project, so I’ll never know if the discrete 16x16 multiplier will ever work. Maybe I should order it from JLC just for fun.
Martin