Many thanks the detailed explanation. I now see why you added a chip outline/pin1 marker over the pads as its not going to be on the board
Yeah, the board looks like this when it’s made (the pin 1 marker under the IC is frowned upon, but for the time being I have them):
(matte black, HASL)
No worries that the fab outline or anything is a problem, they only help you during layout and for documentation.
I just completed the layouts and was trying out your suggestion of moving the references to the Fab layer. When I create the PDF plot, I only get separate sheets for each layer viz, courtyard, fabrication,silk screen. In your attached image, I see the fabrication/courtyard layers being superimposed on the tracks - I refer to the black and white image - how did u achieve that?
That’s how I do that for documentation at the moment:
Also, if you’re after assembly instructions printouts I got this thread for you (directly linked to the nice post by @twl)
Many thanks, I gathered from another thread that you use Elecrow for fabrication - their Silkscreen text size specification states 32mil which is roughly 0.8mm. Can you let me know whether any lines drawn on silk screen has to be 0.8mm width? Or what is the acceptable line width on silkscreen layer considering that I will be using Elecrow?
I use lines that are 0.15 mm wide and they work as you can see.
Looking at those with a microscope (seeing the print screen effect of tiny dots appear) it should be possible to go to 0.1 mm width without trouble IMHO.
Expect alignment faults of ~0.1 mm in any direction (same is true for the soldermask).
PS: …avoid circles and arcs on Silkscreen.
They seem to change fab house at will (in the past) and one of them wasn’t able to produce those, so I didn’t had pin #1 markers on a board.
Thanks for the tips, I think they and all the Chinese website based PCB fabricators just run around with the order for a real PCB fab house which have excess capacity on a given day and get it done.