Newbie Q: Net pad clearance what exactly is it?

I added a hasty keepout layer for the copper pour just to see whether it is having a issue, the redline is the keepout area border

Screen shot as requested below.

Design rules file

I have figured out the issue, the issue is with the track clearance which results in pad near pad error. I managed to change the track width on pad 5 to 0.21mm earlier it was 0.26mm with this I got rid of error between pad 2 and 5

The track on Pad 6 and Pad 3 belongs to RFDummy net which starts thinly at 0.21mm and becomes .366mm but I guess the clearance for the thin part is still retained from the appropriate net list.

I have tried moving the thicker track away from the footprint and connecting with a thinner trace (albeit with the same clearance) - this doesn’t get rid of the errors.

Is there a way to reduce clearance for the thinner part of this net.

The mod file doesn’t get uploaded it keeps on showing uploading 100% but nothing happens, waited for a pretty long time.

Please download

DRC report
** Created on 2016-08-25 09:03:09 **

** Found 3 DRC errors **
ErrType(19): Pad near pad
@ (147.140 mm,111.000 mm): Pad 1 on F.Cu, Non-copper of U1
@ (148.070 mm,111.000 mm): Pad 6 on F.Cu, Non-copper of U1
ErrType(19): Pad near pad
@ (147.140 mm,111.500 mm): Pad 2 on F.Cu, Non-copper of U1
@ (148.070 mm,111.500 mm): Pad 5 on F.Cu, Non-copper of U1
ErrType(19): Pad near pad
@ (147.140 mm,112.000 mm): Pad 3 on F.Cu, Non-copper of U1
@ (148.070 mm,112.000 mm): Pad 4 on F.Cu, Non-copper of U1

** Found 0 unconnected pads **

** End of Report **


If you look at the clearance indicator lines, the inner channel is tighter, so you might want to tune the finger lengths.

Many thanks, I have now resolved this.

I think this is a newbie error mainly attributed to the use of OPENGL canvas which doesn’t show the clearance of the tracks. On top of this the PAD near PAD error code confused me to go and fix things incorrectly.

What I don’t understand is that you set the track clearance to 0.21, when your fab house is able to do 0.2?

Loaded your footprint… Why did you put it off-center?

You also set local pad clearances… I hope you got rid of them now and those were just for ‘bughunting’.
One also doesn’t usually use text to mark pin 1 on silkscreen :wink:

That’s how I would make it (KiCAD standard would put REF field onto silk as you had it, but I don’t have them there):


Your placement outline is also pretty faint… sure the fab can do 0.05 mm?
Reference and value field are being populated by the schematic… the footprint should have them as **REF and **VAL.

The device itself is actual really really tiny. You’re going to reflow that? And you’re a beginner? Hat’s off to you sir and good luck :wink:

PS: I can’t upload other files than images either… just tested. The big boys of the forums got a message from me… we should sort this in due course I guess.

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Thanks for the tips, the reflow will be done by the fabhouse itself, they offer PCBA as well - I needed to test a PA and LNA and the evaluation boards were not available hence just trying my hand on making them - either way even if I do few iterations they will be cheaper than buying the EVB’s and the added gain is PCB design knowledge.

> The fabhouse states
>     Minimum PCB track  6mil (Recommended >8mil) 
>     Minimum Track/Vias Space  6mil  (Recommended >8mil) 

>     Minimum pads Space 8mil 

`Minimum silkscreen text size is 32mil Regarding silk screen thickness - I have to correct it

I didn’t want to test their limits on track width and clearance hence used my own higher limits to warn me.

I have removed the local pad clearances

8 mil is 0.2032 mm, so I can see where 0.21mm came from.
I would put in the exact value, 0.20 mm is just a little too fine

We found the issue on that one: ‘µ’ isn’t appreciated by the system, if you swap it for an ‘u’ the file uploads without issues.

How about U+2126, the Ω symbol?

Same, file doesn’t upload with that symbol in it’s name…

I notice that you have references on the Fabrication layer - what is the signification of this compared to having it on Silk screen layer? Other than visual cleanliness is there any fabrication significance?

Is there a quick way to move all the component references on the populated board to Fabrication layer instead of messing with individual components.

You have two REF** in the footprint one on Fab layer and another on Eco1.user in this footprint - is it just to show me that you can move it to any of these layers or is there more to it?

Reference on silkscreen and Fab layer is there to help assembly/repair. Silkscreen will be placed where it can, but Fab layer reference is usually centered on the component and is more clear. To me, the Fab layer is useless without references.

As @jwpartain1 says, I don’t do references on silkscreen as the devices are so small, there seldom is space for it (or I just don’t want it to be there in the first place).

There are two ways to get values and references from the schematic into the layout… one is via **REF/**VAL and the other is %R and %V.
The former react to the render tab settings and can be used only once per footprint, while the latter are bound to the layer and can appear as often as you want (different layers).

Images following show same area as example…

Now, when I do create documentations I want the Ref+Val to be visible together with the Fab outline layer (and readable = relatively big) but don’t have them distract me while layouting…

(device values aren’t cleaned up yet, thus they’re so content rich as the current library conventions force me to do… for example that C106 would just be ‘100n’ instead of ‘C_100n_50V_X7R_kemet_0805’ if done properly)

During layout I don’t want to see them though (but the fab outline) so I put **REF/**VAL onto the fab layer and switch them OFF in the render tab (out of the way so to speak).
Now… how do I get a ref designation during layout to help me? (that is small + not in the way + sticks out if I look for it) - right, by using %R on a custom purpose layer like Eco1 with a nice color :-).

PS: I only use my own libraries with atomic parts (=each part I use is defined as a symbol and has a footprint pre-attached, I don’t use cvpcb to assign footprints to symbols). That’s why the part names need to be so detail rich, as otherwise the library algorithm fights me…

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Many thanks the detailed explanation. I now see why you added a chip outline/pin1 marker over the pads as its not going to be on the board

Yeah, the board looks like this when it’s made (the pin 1 marker under the IC is frowned upon, but for the time being I have them):

(matte black, HASL)

No worries that the fab outline or anything is a problem, they only help you during layout and for documentation.

I just completed the layouts and was trying out your suggestion of moving the references to the Fab layer. When I create the PDF plot, I only get separate sheets for each layer viz, courtyard, fabrication,silk screen. In your attached image, I see the fabrication/courtyard layers being superimposed on the tracks - I refer to the black and white image - how did u achieve that?

That’s how I do that for documentation at the moment:

Also, if you’re after assembly instructions printouts I got this thread for you (directly linked to the nice post by @twl)

Many thanks, I gathered from another thread that you use Elecrow for fabrication - their Silkscreen text size specification states 32mil which is roughly 0.8mm. Can you let me know whether any lines drawn on silk screen has to be 0.8mm width? Or what is the acceptable line width on silkscreen layer considering that I will be using Elecrow?

I use lines that are 0.15 mm wide and they work as you can see.
Looking at those with a microscope (seeing the print screen effect of tiny dots appear) it should be possible to go to 0.1 mm width without trouble IMHO.
Expect alignment faults of ~0.1 mm in any direction (same is true for the soldermask).

PS: …avoid circles and arcs on Silkscreen.
They seem to change fab house at will (in the past) and one of them wasn’t able to produce those, so I didn’t had pin #1 markers on a board.

Thanks for the tips, I think they and all the Chinese website based PCB fabricators just run around with the order for a real PCB fab house which have excess capacity on a given day and get it done.