In kicad 7, can you set net classes differently for inner layers? How? Looking at past similar topics I could not find a way.
Net classes are a schematic concept, and rules for those netclasses are enforced by PCB rules.
What are you trying to acheive in PCB ? please describe.
You can enforce specific rules on specific layers for a netclass using A.netclass and B.layer sort of constraints
I’ll get back to you shortly with some examples that actually work.
Working on a complex circuit with few high voltage nets that require adequate spacing. However spacing requirement is different for outer layers vs inner layers and I don’t want to use the “outer” number when running a trace on an inner layer.
Yeah so as Glen is hinting, you’d use one netclass for the whole net (or all of your HV nets) regardless of what layer it’s on. Then you’d write DRC rules that apply just to that HV netclass that set different widths/spacing for that netclass depending on what layer you’re routing on.
(NOTE version : K8rc2 )
this works. dont forget we use A for both, since the interest is both the same object
(rule "trace width top "
(condition " A.NetClass == 'HV' && A.existsOnLayer('F.Cu')")
(constraint track_width (min 0.3mm)))
this also works
(rule "trace width inners"
(condition " A.NetClass == 'HV' &&( A.Layer=='In1.Cu' || A.Layer=='In2.Cu')")
(constraint track_width (min 0.3mm)))
And this worked capturing ALL inner layers 
(rule "trace width inners"
(layer inner)
(condition " A.NetClass == 'HV'")
(constraint track_width (min 0.3mm)))
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(NOTE version : K8rc2 )
AND
you probably want a wider copper pour clearance on an inner layer … sooo
(rule "HV zone clearance inners"
(layer inner)
(condition " A.NetClass == 'HV' && B.Type=='zone'")
(constraint clearance (min 1.0mm)))
and you probably want a general smaller clearance, perhaps, this would need to go before the zone clearance so zones are hooked as the last thing it checks
in this order
(rule "HV general clearance inners"
(layer inner)
(condition " A.NetClass == 'HV' ")
(constraint clearance (min 0.7mm)))
(rule "HV zone clearance inners"
(layer inner)
(condition " A.NetClass == 'HV' && B.Type=='zone'")
(constraint clearance (min 1.0mm)))
you can see it applying the smaller clearance boundary thin green line for other than zones
Hey gkeeth I am getting the hang of this !
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Guys, thanks a lot! Is there a tutorial, video explaining how to accomplish this?
Problem is I’m a hard core analog designer. I’m allergic to programming, coding, anything of that nature. Even digital circuits.
Suggest use Kicad 8 RC2 if you are big on rules, like me, there have been substantial enhancements in 8.
.
Read the custom rules section in the PCB doco and come back to us.
It’s easy once you get the hang of it, done inside the PCB editor.
custom design rules help link :
You have to write rules and understand them. As you’ve probably written custom rules in Altium, you’ll understand.
If you like my suggestions, please accept as solution.
This is promising. It’s not just clearances that differ. Current rating of inner tracks is lower than on the outer layers. Time to experiment on the release candidate
I’d bet that inner layer breakdown is higher due to the prepreg completely surrounding the trace, compared to on outer, there is an air path. But that’s a guess. I usually relax inner layer clearances anyway.
Inner layers don’t have to deal with surface contamination, so much better for high voltage safety
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Here is a handy tool for spacing:
For example, 500V requires this:
I have already asked myself the same question. The current rating doesn’t matter in my opinion, because I choose a suitable trace width. For inner layer, I can choose a wider trace. But the spacing to filled zones is automatically generated based on the settings and they only differentiate between the assigned net, not the layer. moreover not all layers must have the same thickness and therefore different minimal line width and spacing. Assigning nets to net classes isn’t a solution, because layers are connected together, so some signals extend over different layers with different thickness.
I never used the custom design rules. Can I handle this task with the custom rules?
There are a lot of new DRC rule features in v8, but all the stuff discussed in this thread was present when the DRC rules were first implemented in v5.99/v6.
I’ve been watching this show and observe the following:
(OP: @SMPS )
-
OP wants to set Net Classes based on Layers
-
OP wants adequate Spacing based on Layers
-
OP does Not want to fuss with Coding, Programming, anything…
-
OP indicated desired Gaps between Traces
Unless I’m blind or too ignorant, aside from a few posts re DRC and other info not specific to OP’s posted Question, It seems a simple approach for OP to consider is to simply:
- Draw the Traces on desired Layer’s
- Can set & select Trace (track)-Widths in the Pull-Down
- If OP is using DP (Differential Pair) the Gap can be set in panel by clicking the Green PCB Icon on top of Menu-Bar (there’s a field for DP Gap)
- Can Create the NetClass’s by Entering a New Net name in the popup and Can Set Tracks to desired NetClass by clicking: Inspect>Net_Inspector and Selecting and/adding a Net.
- Can assign a Net to Tracks (individuially or by multiple selection (Window-Boxing and/or appropriate keyboard keys)
(Can Hide layers to avoid selecting Traces/Pad/etc. Then set them to Visible when done)…
ADDED:
The items could be Tracks, Polygons…
This shows Tracks on each layer and Creating/Setting them to NET’s
(the first click is to change their width for visual clarity)
Can set Track Widths/etc in the same Panel (buttons for selection, layer…etc options.
Black coffee, I’d have have to disagree,I think that’s not an extensable way to do things. That’s doing it retrospectively. Inside of having firm limits and constraints you must live by from the start
SMPS you probably just need a dozen custom rules.
We’ve got a few done already. Assign the netclass names (and label in your schematic) and constraints etc on layers that you need, and I will write the rules for you.
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