My GND net name gets eaten by another net name on the PCB

[Piotr]

@osterchrisi

But the KiCad 6 documentation states this:

You should mark yellow only last sentence: “the net name…” as two previous work as written.
I suppose that someone writing that sentence was thinking about connecting element pins to Power net and that Power net name (like GND) takes preference over any other net name that can be deduced from element reference + its pin number. So you will see GND instead of randomly selected net name.
If you give explicitly the other name to GND net that there is nothing wrong in KiCad assuming that you want to rename it. And only the documentation can be updated a little.
I hate programs that know better then me what I want so I agree with KiCad behavior: User wants to give other name to GND - program shouldn’t defend him.

[hermit]

I’m not sure how I feel about this. Is this an argument about when are you offered too much choice? Things like GND are a standard of sorts. The problem is if you are allowed to accidentally over write them. Even intentional might not be the best idea.

But, then we have the concept of consistency. Can I, or can I not, over write net names? I before E except after C… Carving out exceptions is its’ own can of worms.

[celem]

I’m using 6.0.9 and this is the behavior that I see. My project has five different voltages present as well as several different trace widths due to multiple current requirements. I ended up using Net-Ties to to get everything connected correctly. I had to create modified versions of the Net-Ties to have them be sized right. I disliked having to add copper simply to overcome this Kicad behavior. I’ve heard that a virtual Net-Tie is being considered that solved this problem without laying down additional copper.

[pedro]

Six days ago I sent a link to an older thread. As I guess you did not read it, I copy it here:

For reference, the precedence for generating net names from labels is, from lowest priority to highest priority:

The name of a pin on a non-power component
A local label
A heirarchical label
A pin label (i.e. the “+3.3V” from a power pin)
A global label

[eelik]

And in case of otherwise same priority, the alphabetical order. It, too, from lowest to highest priority.

[osterchrisi]

For completeness: KiCad’s documentation was updated. There is now a beautiful new section: Net name assignment rules and it clears the rules once and for all. Well, for now anyway

I’ll quote it here:

Net name assignment rules

Every net in the schematic is assigned a name, whether that name is specified by the user or automatically generated by KiCad.

When multiple labels are attached to the same net, the final net name is determined in the following order, from highest priority to lowest:

1. Global labels
2. Power ports
3. Local labels
4. Hierarchical labels
5. Hierarchical sheet pins

If there are multiple labels of one type attached to a net, the names are sorted alphabetically and the first is used.

If a net travels through multiple sheets in a hierarchy, and has no global label or power port, it will take its name from the highest level of the hierarchy where it has a hierarchical label or local label. As described above, local labels take priority over hierarchical labels.

If none of the labels above are attached to a net, the net’s name is automatically generated based on the connected symbol pins.