You didn’t read carefully what I wrote, or what Jon wrote.
The order is strictly deterministic, and you can’t expect that just adding a new global label works in all cases. When there are several global labels, they must be sorted somehow to find the winner, and the alphabetical order is meaningful here, but so that G loses to O.
EDIT: and by the way, I agree with Piotr:
Adding more names to one net only adds to the confusion. If you want to use a net named GND, then keep the plain GND symbol and if you want to add labels, give them all the same name. If OP_AMP_+_2 is the same as GND, why not call it GND? If the connection point between what is called OP_AMP_+_2 and the rest of GND is controlled, use a net tie.
Why not draw it like this? Hierarchical net names are not really meant for indicating a connectors pinout anyways, all though usually it’s conveniant to do it. You can indicate the pinout with text close to the connector?
…which wasn’t followed up. I believe this is a misconception of schematic. I also later realized that the opamp is on his schematic, not on a connecting board on the card connector.
The next comment I don’t actually understand:
Given that a schematic, once drawn, is permanent, I don’t see why it’s important to keep the reference on the connector if it’s always connected to ground on the component. If, on a later revision of the board, one would want to connect a resistor to the pin instead of straight ground connection, you simply do that and re-instate the opamp-naming on the connector pin net.
Btw. @osterchrisi , if I understand your design correctly, you are making an “opamp daughter card” of some sort? Since you put the name of the pin on the connector, isn’t it counter intuitive to have it “pre-connected” to ground? Why not let the motherboard decide the connection?
Thank you everyone for your efforts to help out. Like stated earlier, I am specifically NOT looking for advise on drawing schematics or layouting a board. It seems like everybody is making their own assumptions about their own workflow being the solution to this issue. In my initial post I have given all necessary information to answer my question, which was also stated in the first post.
It feels though as maybe some users would feel better appreciated if I point out WHY I need to work around what still seems like a bug:
I am designing a cartridge for an open source project. This is a project that spans several teams, countries and software programs. I cannot control the cartridge connections nor their name, order or pinout. My schematic should later be published publicly and should be legible by anyone who was not a designer of the “motherboard” and therfore has no knowledge about which cartridge connections from the motherboard carry which electrical signals.
If I follow some users’ suggestions here, I would create a situation where downstream some interested person looking at my schematic might be fooled into thinking pin 19 carries a ground connection when in fact - if no cartridge is connected - it connects to the pin of an opamp.
I hope this clears up my disinterest in solutions suggesting changing my workflow.
Also, no offence to anyone please. I find it hard to find precise words and keep the conversation on topic without potentially sounding like a d*ck.
Is this because the comparison ends when the last character in the string, ‘GND’ in this case, is reached ? (I am assuming the string is compared character-by-character with each of the possible names, starting with the starting character and ending when the end-of-string character is read, before a match is declared.)
I have questions I need answered before coming up with more suggestions. Can you share some more of the OSHW design you are mating with?
All my suggestions are well meant, if they don’t suite you that’s fine. But if I spend the time to suggest something for you I hope you read and consider it even if it’s a suggestion to change your workflow. Because if you have bad workflow, why not change it? I don’t see that the constraints given by the OSHW project actually constrain you that much, I think this can be solved in many other ways then directly tying a global net to ground. Which in itself can be confusing to a reader.
Considered just leaving the connector pin floating?
Your daughter card has the opamp on it, and if you remove your daughter card from the OSHW board then no opamp is connected to the OSHW board, right? Then why
?
You mean fooled into thinking pin 19 on the OSHW project also carries a ground connection? Because in the case of your design, he is not fooled, he’s right. Wouldn’t it be solved by putting some text on the pin, indicating what the pin is used for?
Attached I have a picture of a component in Kicad component library called net ties. I think they do what you want, but I’m not sure if consideration must be taken to remove it from netlist and exactly how it translates to PCB editor. Have a play around with it? Recommend to check the two boxes as indicated
No, it’s the other way around. The opamp sits on the motherboard and I can use it on my cartridge via the pins (which I do). This is also why I draw the schematic in a way that makes a future reader understand what is going on (second screenshot in my initial post) - the connections with the labels somewhat representing a “ghost opamp”.
I already tried the NetTie component and it does the opposite of what I want - it’s somewhere in the middle of the thread.
To really boil down the issue to the most atomic version: Why does this result in a net named “WHY”?:
Well, this was explained several times. An explicit global label overrides the GND name. This may be a matter of opinion or taste, but in my opinion explicit should override implicit, it’s good.
It might be easier to discuss this if you would attach your KiCad project here. But to me it looks like you have some problem with the “workflow” even though you state otherwise. Maybe you are trying to use a feature of KiCad for something it’s not designed for. For example: global labels are for a KiCad design, they don’t need to be identical with some pin name of some external component. Why can’t you control the global net name? It’s not meant to exchange information between some other KiCad project or some other external program or project.
Prepending the name with . or _ would solve the problem because then you could add another global label named GND for that net.
And reading from your first post, your problem seems to be the net name in the layout, not in the schematic. Why is it a problem? It’s just a layout, and if someone else edits it, they must have the schematic, too, and the schematic is the source of the functional understanding of the design. Or you could add an extra global label to that net called XGND which would convey the meaning well enough and would be seen in the layout without changing the other global label.
You should mark yellow only last sentence: “the net name…” as two previous work as written.
I suppose that someone writing that sentence was thinking about connecting element pins to Power net and that Power net name (like GND) takes preference over any other net name that can be deduced from element reference + its pin number. So you will see GND instead of randomly selected net name.
If you give explicitly the other name to GND net that there is nothing wrong in KiCad assuming that you want to rename it. And only the documentation can be updated a little.
I hate programs that know better then me what I want so I agree with KiCad behavior: User wants to give other name to GND - program shouldn’t defend him.
I’m not sure how I feel about this. Is this an argument about when are you offered too much choice? Things like GND are a standard of sorts. The problem is if you are allowed to accidentally over write them. Even intentional might not be the best idea.
But, then we have the concept of consistency. Can I, or can I not, over write net names? I before E except after C… Carving out exceptions is its’ own can of worms.
I’m using 6.0.9 and this is the behavior that I see. My project has five different voltages present as well as several different trace widths due to multiple current requirements. I ended up using Net-Ties to to get everything connected correctly. I had to create modified versions of the Net-Ties to have them be sized right. I disliked having to add copper simply to overcome this Kicad behavior. I’ve heard that a virtual Net-Tie is being considered that solved this problem without laying down additional copper.
For completeness: KiCad’s documentation was updated. There is now a beautiful new section: Net name assignment rules and it clears the rules once and for all. Well, for now anyway
I’ll quote it here:
Net name assignment rules
Every net in the schematic is assigned a name, whether that name is specified by the user or automatically generated by KiCad.
When multiple labels are attached to the same net, the final net name is determined in the following order, from highest priority to lowest:
If there are multiple labels of one type attached to a net, the names are sorted alphabetically and the first is used.
If a net travels through multiple sheets in a hierarchy, and has no global label or power port, it will take its name from the highest level of the hierarchy where it has a hierarchical label or local label. As described above, local labels take priority over hierarchical labels.
If none of the labels above are attached to a net, the net’s name is automatically generated based on the connected symbol pins.
