Musical chairs with Electrical Rules Ceck

I am trying to finalize the schematic for my project

Whenever I run an Electrical Rules Check I get an error message, this one for the error arrowed above (Pin 1 on RC1)

If I fix that, usually by redrawing the trace, the same error pops up somewhere else next time I run a check. I’ve done about three laps so far and Ahm Plumb Wore Arrt! How can I stop this game of Musical Chairs?

You need to add power flags to your VDD and ground pins at the barrel jack to tell the ERC that there is a power supply to these pins

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This was explained to you previously in at least two other threads. Why do you continue to ask the same question? Re-read the answers you got in those previous topics.

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We now also have a very good FAQ article that explains this: ErrType(3): Pin connected to some others pins but no pin to drive it

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The best solution: Not run Electric Rules Check. I am serious.
I have never run Electric Rules Check. You (as an author of circuit) know what have to be connected to what. No computer will tell you that you have to do something just to satisfy ERC. This way during designing my symbols I need not to spend time on assigning electrical parameters to pins.


Only people who really know what they are doing should ever try to ignore ERC! Yes sometimes it gives false positives but god damn how often i repaired a PCB build by somebody who thought he can ignore ERC (or DRC for that matter) is staggering. (A hint 100% of the people i have teached so far had a real problem behind an apparent false positive. In other words: They thought they can ignore ERC -> Result: non working PCB.)

This is just bad advice. Even if you talk to someone who is really experienced. Telling that to somebody who does not even understand what ERC is does not help anybody.

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Your overlooking its function, I cannot say the scale of the projects you make, But get into anything high density or complex, having something give you a basic idiot check, is a net benefit.

Its current iteration is not as advanced as some other tools, e.g. differential pair skew, but in almost all cases It has caught out small things I may have missed, e.g. pin 24 is meant to be connected to something, not having a no-connect there caught it, rather than me getting to final layout verification to catch it.

I don’t remember ever having the situation when the same error pops up in a different place each test, continuing in a circle until you are back where you started. The only power output, and the only earth output, are on the Barrel Jack - all the others are inputs. The trace connections have all been double-checked. The electrical parameters are, I think, all okay. My only confusion there is that I am unsure of the difference between passive and bi-directional. This does not explain continual re-appearance.

passive you can treat like (no conflict), where bidirection is an input that can drive inputs.

a connector generally would be passive, but if your connecting to a module that you know the pin mapping of, you can set up the power inputs, outpus, inputs, etc so that it flags any issues

warnings are things for you to assess as a designer, and fix or agree with, errors should be fixed in most cases

Yes it does, and this was explained to you, I know because it was I who explained it. The error may apply to many pins on the same net but KiCad will only report it once. Which pin it chooses to report the error is up to an internal algorithm. If you change something on the board it will quite likely pick another pin on the same net the next time it reports the error. It all comes back to the same issue, which again was explained by several others, you have one or more power inputs on a net but no power outputs to “drive” them.

An extremely bad idea. Even those who “know” what they are doing make mistakes. ERC, although not perfect, helps provide a bit more of a sanity check.

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That nailed it. Thanks.

@1.21Gigawatts, @Vagulus and some more characteres

I didn’t wrote about DRC. I always run DRC.

I am here since short time. I have seen few questions regarding ERC and I think always schematic was good but needed only to add power source markers to satisfy ERC. I sow (probably at same link given here) that someone defined socket pins as being the power source to satisfy ERC what in my opinion is stupid.
I suppose you are here since always :). Have you ever seen questions regarding ERC when it was really a schematic error?
I think you can do many serious errors while designing schematic (DCDC unstable feedback, wrong ESR of capacitor at LowDrop output, wrong resistor divider for specific voltage, lack of capacitors with crystal, too weak driver circuit of power MOS gate, too low dv/dt at digital input without Schmidt, too high power dissipated at resistor/diode/transistor/…, and many, many more…) and I think most of them would be not noticed by ERC.
Thet way in my opinion passing ERC in many cases (specially for baginners) can give them false feeling that everything is OK.
I remember only one situation when my PCB has to be redefined because of my error in schematic. But ERC wouldn’t helped. I was using temperature digital sensor (destined to switch on fan) to switch on heating. As I remember in datasheet they used words like output is activated or not and was not sure when it is high and when low. And I inverted logic I needed.

Yes. The first post by @Vagulus was one example :wink: (And the ones from people i teach at university)

I supposed it was also the problem of only power source markers. I will check to see if I need to read more carefully.

When I was a student I forced teachers (there were two for one difficult excercises) to change the credit rules. At the beginning they said you need at least 50 points per 100 from tests and 3 absences disqualify. I had 5 or 6 absences (term colided with my tasks as canoying club master) and got 99 points. At the end they said that they understood that study are not school and counts what student knows and not if is present (they also had a tradition to give 3,2,1 points extra for activity at excersises and said that when I was I always was the best so I’ve got 3 so my end result was 102/100 :slight_smile: ).
After study I teached students. After 3 years my older collegues (carrying the same excercises (linear circuits theory) with other student groups) asked me how am I doint that that my students are always the best at exam (all groups together). I didn’t know that enyone made such classification. They told that they would have told me that if my students were not the best. They supposed that I by chance got the better students groups. After 3 years they thought that must be different explanation :slight_smile:

My projects are not very complex. One microcontroller (64 pins) with interfaces (OC input/output, relays output, Ethernet, RS485, RFID, ZigBee, LCD, touch pannel, touch keyboard) powered by DCDC accepting input 8…30V (assuming overvoltages up to 50V (33V transils)).

I think such error is 0,01% chance. When you draw elements around that IC you see its application in datasheet. My microcontroller has many pins which I left unconnected (in one device I used all and it is a problem) and not using ERC I just left them without any my action.

May be my thinking is because:

  • when I begun I had no access to PCB software (painted PCB by hand) so no ERC possible.
  • when we start to use Protel someone else worked with it and I gaved him ballpen drawn schematics and then get it printed to verify,
  • when I took designing PCB (because of EMC) I have never found ERC (used only functions needed and never serched for others - I concentrated on PCB and not on schematic where I didn’t know of any problems possible).

In my opinion it is very, very small bit (if bits has sizes :slight_smile: ).
I think it is very hard to make mistake ERC will find comparing to mistakes it will not find.
But I design ony microcontroller devices - really each pin can be input or output or left unconnected. ERC would only force me to add crosses to many pins. And when during PCB design I will select other pin for specific task (I do it many times in each project) I will have more work with these croses.

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