I have uncovered a situation that I think may be indicative of a KiCAD problem. When using multiple power supplies and using a logic symbol from the library, KiCAD incorrectly connects the power nets together. I have attached an example below. In this case, there are two power supplies supplied from two different batteries. Each logic gate has its power pin connected to the battery supply. When I highlight the net, both nets are highlighted indicating the net are connected. Moreover, when I run an ERC, the ERC indicates these nets are connected and provides an error indicating the associated PWR_FLAGS are conflicting. The intention is to keep these two power nets separate. If I disconnect one of the logic gates from their respective power net, the two power nets are no longer connected.
When I looked into the symbol for the logic gate, the power pin is defined as a power input and the pin name is VCC. I understand KiCAD uses the pin name of the power pin as the name for the connected net. So, what appears to be happening is KiCAD is connecting the separate power net together because the pin name (VCC) is the same for these two instances of the logic gates.
Is there a workaround for this issue? I suppose I could create two separate symbols for the logic gate instances and rename the pins VCC1 and VCC2. This is not the preferred workaround. I actually have another two power supplies and other components in the schematic. So, this workaround would require new symbols for every instance of a component that had a power pin named VCC. I am hoping there might be another suggestion.
We are aware of this restriction. Which is why for example the Logic_4xxx and Logic_74xx libraries no longer use hidden power input pins but place them as normal pins on an additional unit.
We did not have the manpower to fix the rest of them so well you need to fix it yourself (in your personal lib).
I wrote a description on how this can be done back when v4 was the current stable. You can take it as an inspiration (the general idea is the same but the symbol editor interface is different) IC footprint VCC+GND
The 74AUP logic gate I am using does not have a hidden pin and I can connect a separate net to the pin. The problem is the pin is named VCC which causes the conflict with another instance of the logic gate or any other component that has a power pin named VCC. This appears to be a limitation when using circuits with multiple power supplies (1.8V, 3.3V, 5V, etc).
Are you aware if this issue is addressed in v6? I saw a reference to a similar problem but it appears to not have made it into v6?
The symbol as in the library has its vcc and gnd pins hidden. Your screenshot also suggests that they are hidden (otherwise the pin names and numbers would be visible for them). And i know for certain that ONLY invisible power input pins are global labels.
Ahh, I see what you mean. I mistakenly thought because I could see the connection point when it was unconnected the pin was visible. In fact, the pin was not visible. If I change the visibility, that ensures the net is not a global net as you indicated.
