@jmk, yes, I found ages ago how to set the drill and grid origins to where I want them at the lower-left corner of the board, and set y-axis-up. Else this would have driven me crazy
I still don’t see why I would want to use net classes, as I just have my lists of widths and vias I like and change them as I work.
However, I have now found an oddity related to net class. I generally use 0.2mm as a min clearance, but in a current board I am using a sot563 and clearance between pads is 0.18mm. In my Board-Setup/Design-Rules/Constraints/Copper-Min-Clearance I set it to 0.18mm (or even smaller) but still get DRC errors:
Then I find that the error is related to net class, which I did not think I was using:
Well sheesh, ALL of my traces are default net class and there is now ANOTHER setting I need to set for copper clearance:
I presumed that Board-Setup/Design-Rules/Constraints/Copper-Min-Clearance was THE master value, but this net class setup, which I never touched since I never used them, needs to be changed also so I can pass drc. Am I missing something?
I don’t use erc much, since power errors just get silly (I know I can turn them off in violation severity). I don’t want to clutter the schematic with flags every time I go through a connector, or switch, or ferrite bead (and I use a lot of ferrite beads). Yes, it is great to find connected outputs or a floating cmos input now and then, but I don’t expect much from erc.
DRC on the other hand is really vital to catch oddities, so I want to explore and fix drc errors. I don’t mean to hijack this thread too far beyond the OP’s question, though sometimes these topics just meander in related directions.