I doubt that this circuit based on a simple op amp (LM741) can work properly to measure ECG signals.
ECG voltages measured across the body are very small. These low voltages usually need instrumentation amplifiers to obtain a correct signal conditioning.
I know nothing about their level but may be they are not so small as high impedance. CHEST1 input impedance is about 10M. Signal is multiplied around 50 times and then it goes to soundcard which is quite a sensitive input. What is amplified is difference between CHEST1 and CHEST2 (and differential impedance is 10M). Instrumentation amplifier gives high impedance at both inputs. Here we have it only at one input, but may be it is enough. RIGHT_LEG looks like reference GND probably making visible at output noise smaller.
OpAms are powered from +/- voltages against GND. If you have one supply you make ‘virtual’ GND by making a mid point between supplies. Here RIGHT_LEG is 'virtual’GND.
Ground plane will not help you a lot here.
GND plane works against waves with wave length in the range of GND plane size. 1GHz has wave length of 30cm. 30cm GND plane will have very small noise eliminating effect starting from may be 1/100 of 1GHz so from 10MHz and then the higher frequency the higher effect. It can filter out radio frequency disturbances, but your circuit should have so limited bandwidth that it should not see such frequencies at all.
For 1Hz wave length is 7.5 times the length of the earth’s equator.
It’s a common mode rejection ratio issue. I wish I could get a decent signal with this setup. It would have saved me a lot of money 
I’m sure of nothing, but LEGS are used as reference in these measurements. If we have ‘virtual’ GND connected with LEG=reference than may be we don’t have to worry too much about CMRR specially as output signal shape probably needs not to be compared with exact shapes known by doctors. Here we just only wants to have something like signal, I think.
Yes and no. I design eeg circuitry with signals down around 1 uV (ecg is more lax at around 1mV). My signals are digitized and streamed and when I crunch an fft I see my signal ground floor at more than 100 dB down, (which is under a microvolt) and powerline noise is noticeable above that. Yes, much of that is due to common-mode on signal cables and inamp or diff-adc mitigates a lot, but the pcb circuitry is not immune to LF noise pick up. I can definitely see the difference in 60Hz residual as my board revs change with improving ground planes. BIG difference between a rev only having planes on inner layers and a rev that adds flood fill-in on top/bottom as well, with stitching vias. I put ground fill on EVERY board. Yes, wavelengths are of interest at emi freqs, but noise pickup on low-level analog also has capacitive/inductive coupling mechanisms. I am no expert on the physics, but I know that generous ground fill is always beneficial.
Also typical in ecg is right-leg-drive, where the powerline average from signal channels is fed out-of-phase into the leg body ground. It is the same concept as noise-cancelling headphones.
There is also a problem of demodulating RF at any semiconductor even in low frequency circuit. Good GND plane (and shielding) minimizing RF picked up by circuit minimizes effect of those demodulation. But here we have simple DIY circuit and not the problem with signal ground floor but the problem that it worked in prototype and it doesn’t work in next prototype. GND plane has little or no influence on it.
If ecg are 1mV then multiplied by 50 it is 50mV. It should be enough to show by soundcard (I suppose input is about 1Vpp so 1/20 of full scale looks being enough).
Yes, you are right – gnd plane won’t fix that broken circuit 
I can understand in the “ before “ but with pcbs a few bucks from China , for full featured pcb including 4 layer , why is a give milling their boards
First post in this thread was Jan 18.
Then after information that tracks should be wider the next post with new PCB photo was Jan 19.
I suppose it might as well be an hour past first few answers.
I have never ordered anything from China. I would expect that custom could halt my packet and want me to fill out some paperwork that I have never filled out before and then pay some duty or VAT.
Time spend on it can be accepted when you need 4 layer PCB, but as you need one layer…
Poland is also within the EU I guess, and most companies that deal with the EU from outside of it do the paperwork for you and VAT is included in the price for orders below EUR150.
Theoretically, you are right, but since 2015 we do everything to have a law that is incompatible with the EU 
Oh well there are always people the opposite to the flow
Hello
Regarding,
“I´m building a project that I tested on a breadboard and it worked fine. But when I built a prototype PCB it didn´t work well.”
Please tell us are you a student and is this a school project (assignment)? Assuming so, we should not do your work for you but rather advise you how to overcome your blockers so that you understand what is going on.
It might help us if you show a photograph of your bread board. This will help us understand your past success.
I see below that you do not have an oscilloscope. Do you have a multi meter?
There are some tests with a multi meter that can help a lot to figure out what is happening.
You are working with a OP AMP circuit where the signals in are from living tissues and are quite small. This OP AMP circuit has voltage gain of the signal from chest1 to chest2 of -R3/R4. For the values (If I am reading them correctly) chosen that gain is -100K/1.8K or -100/1.8 or about 55.
If you connect the EKG leads for chest1 to chest2 the output at U14 pin 1 should be the at one half the batter voltage when measure with respect to the BATT- lead.
By one half I mean the voltage which is set by the two resistors R1 and R5. Help us understand what you understand. Tell us why the voltage at U1 pin 3 should be at one half the battery?
I hope this helps us help you.
Regards
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Hi @ForrestErickson, I´m not a student. I´m working on this project more as a hobby and wish to learn more about electronics.
This is a picture of the breadboard: I tried changing things around but it only worked with the capacitor grounded somewhere else than BATT- and output connected to the R5 instead of the capacitor output lead.
Yes, I have a multimeter
I believe the reason why the voltage at U1 pin 3 should be at one half the battery because the op amp need +V and -V to function so it´s needed to create positive and negative tension.
Thank you for the reply.
Thanks for providing the picture it helps.
Some help:
As per the advise others have given you, it is good practice to connect the unused OP AMP so that it does not have unexpected behavior. One way to do this is to connect the Non inverting input pin 5 to the junction of R1 and R2 so that the input is biased to half of the battery (Just like the OP AMP you are using is biased but through R3). Then with a 1K resistor connect the unused output on pin 7 to the inverting input on pin 6.
The result will be that the second OP AMP will be what is called a voltage follower and will have on the output the bias voltage.
The big green part is I assume a capacitor however I cannot see the connections.
Can you provide a photo that makes connections clear and tell us to what part on the schematic it corresponds?
Your schematic shows four 0.27uF capacitors in parallel. Is this the equivalent of the green part?
Please measure the voltage from BATT- to the junction of R1 and R2. Please update your schematic to liable this net something descriptive like “Vbias”. If you do not know how to name nets this is a good time to learn and this will help:
Robert Feranec
What is KiCad about? Starting with KiCad …
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Hi, I started working on a different layout for the same project but I´m not sure if it´ll work due to GND connections and vias that take connections to the bottom and front copper plane.
Should GND be connected to each other and work or should I create a ground plane on the back copper layer and drop a via to the ground plane from the GND pad?
This is a picture of the current layout.
In this pictures GND are disconnected, but I connected all of them with traces.
Is it ok to have traces going from front copper layer to back copper layer through vias in the design?
A full ground plane on both sides of the board would be a good plan - stitch both layers together with a heap of vias.
However, the layout is a bit meh, tbh. I spend a lot longer moving components around than routing and I think there are a lot of areas here that you could optimise even if you aren’t trying to fit this on the smallest board possible.
For instance, C4 and C5 could be moved closer to pin 6 of U2, you could rotate R14 & R15, move U1 and U2 closer, rotate most of your passives by 90 degrees etc.