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dear kicad

I have just started PCB desiging
i have few questions relating dividing ground copper layer

i have divided the ground layer in 3 parts
analog ground(AGND)
digital ground(DGND) and
other i don’t know what to say it is a as marked in the picture bellow in red

1329×688 102 KB

3576×2278 1.39 MB

can some one please tell me is that correct way to divide ground layer into 3 divisions ?

Regards

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PM sent about nature of topic.

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Never divide GND.

At least not AGND and DGND.
Use GND plane if possible (and it is on 4+ layers)

Normal usb connector.
Bolt to GND.

I prepare myself for a war on this topic and withdraw in time.

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thanks nicholas

this is 6 layer PCB

ground is on the 2nd layers after front layer
so what you suggest is to have the complete ground copper as ground layer but in my schematic some part of the circuit connects to analog ground and most of the circuit is connected to digital ground and some other is connected to the one marked in red just above USB PC connector

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i personally would not separate the analog gnd from the ground plane

this is me and other may have different opinions
you must understand that for some people design practice about gnd this is worse than religion.

for 6 layer my stackup would be as follow

1- signald
2. gnd
3 - power
4 - power
5- gnd
6 - signal

this way you can make cuts in power planes and it will be invisible for the signals.

also if short on routing capabilities you could route some short traces on power planes.

avoid rows of vias making to long cuts in your planes.

ideally you should have thin prepreg between power and gnd
2-3 mil
mil = 1/1000 inch

sound to me you have only 1 gnd plane

what do your stackup look like ?

8 layers example
1-signal
2-gnd
3-signal
4-power
5-power
6-signal
7-gnd
8-signal

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my stack up is as seen on the right side of the image

1 Front.cu (Signal)
2 Ground.cu(Ground)
3 Routing1.cu(Signal)
4 Routing2.cu(Signal)
5 Power.cu(Power)
6 Back.cu(Signal)

why do we need to have multiple ground or multiple power plane ?
Prepreg thickness is decided by the assembly house correct or do i need to mention it in the pcbnew design if so how ?
as i understand power planes and ground planes are not meant for routing signals due to impedence on these plane signal is attenuated this was well explained in my previous link bellow is the link PCB designing for 6 layer by Joan_sparky and keryseykaryu please see in the beginning of this link?

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thanks andy if i understand it all correctly the stack if i want internal routing will be

1-signal
2-gnd
3-signal
4-power
5-power
6-signal
7-gnd
8-signal

in this case there are two gnd layers one is analog and other is digital ground correct ?

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Thanks Andy so according to you i must connect all analog and digital points of my circuit to the same copper layer called ground.cu and what about chassis where will this be connected to ?

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Thanks andy now it looks clear well in that case i shall not divide the ground copper layer just leave it as it is
now i need internal routing support as well in which case my PCB is 6 layer hardware. so
1 Front.cu (Signal)
2 Ground.cu(Ground)
3 Routing1.cu(Signal)
4 Routing2.cu(Signal)
5 Power.cu(Power)
6 Back.cu(Signal)

  1. is that ok
  2. now what about power.cu since many of my components need different voltage levels do i divide the power copper layer ?
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As you divide your power plants you will get splits.

As traces travels across those splits it may become a problem.

But if all power planes hace low impedance towards GND the signal will not suffer very much.

You will get cross talk between you middle 2 layers depending on the thickness of prepreg / core between them.
Depending on for how long distance traces goes parallel, depending on signal rise times.

Normally one do not bother to open a can of worms unless the pcb is going to do very high volumes.

Then you can justify the time it takes to counter attack the inherent weaknesses and br prepared to trouble shoot and measure in the lab, beacuse the very high volumes justifies this extra development time.

You should always be in control of your stackup.
Material thickness etc etc.
Never allow the Pcb manufacturer to alter trace width beacuse they made some calculations on their own behind the scene.

You should be in dialog with them, but also in charge of your design, it’s your design in the end.

Specify thickness.

A weakness in kicad, we can’t do in the tool.

Use excel sheet.

1 Like
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thanks Nicholas

  1. if i do not divide the power.cu then how will i be able to supply different voltage levels required by different components?
  2. if a trace travels across the split it will be a vertical path not horizontal path then it will be only using via which is copper coated ?
  3. so what would be your stack up keep in mind i need internal routing also bear in mind the cost of PCB manufacturing ?
  4. trace width i am relying on http://circuitcalculator.com/wordpress/?p=25/ my board edge cuts size is 90 mm * 65 mm or 3.5 inch * 2.5 inch let me know if you have any default trace width calculation for internal layers and external layers in air for differencial,digital,analog signals

Regards

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Earlier in thus thread I gave examples of 6 and 8 layer stackup.

If you want 4 layer for routing it’s a 8 layer stackup.

I would actually start with my proposed 6 layer stackup and do routing before jumping to the conclusion that 4 signal layers are needed.

0.1mm trace 0.1mm separation.
0.35mm via pad and 0.2mm drill.

Thats more costly with narrow traces but 6 layers is cheaper than 8.

Yoy are free to do as you want.
I don’t know anything about what actually will be in your design, so hard to give any definitive recommendations.

This before is more of an advice.

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Once you get to 8 layers or more, you are really entering blind vias territory, which limits suppliers and raises costs even more

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maybe

one of my most used stackups for massive ddr designs where we used an asic with like 14 ddr interfaces was 14layers
but there was no need for microvias or bblind vias

goes like this 14L
1 - signal (high speed serdes)
2 - gnd
3- signal 18u
4 - vddq (ddr-io-power) 18u
5 - gnd 18u
7-power 35u
8 power 35u
9-gnd 18u
10 signal (ddr)
11 vddq power
12 signal
13 gnd
14 signal (high sped serdes)

what i noticed lately is that many components can now only be had in 0.5mm pich bga (consumer market driven)
meaning you cannot do break out without micro-via

problm with micro via is that they tack you from F to F+1 or B to B-1

as int the case of

1-sig
2-gnd
etc
your microvia takes you from signal -> gnd and thats not very useful

stackup then needs to change to
1-gnd
2-signal
etc

oh well

always fun with stackups

however dur to the 0.5mm bga i think pcb manufacturers will be pushed into considering micro-via a vanilla thing.