No…I am just looking at all of the error/warning arrows (bright green in my image above.)
You’ll have to cope with the other denizens. They’re an eclectic bunch. 
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I don’t seem to get the same errors when I run my DRC. They’re a modified footprint for a “MountingHole” which I believe is considered a VIA, so that may be why.
One thing I just noticed; I guess that all of your footprints are locked. Probably not a root problem but just something to note for any of us trying to figure out your board.
I think I need to shut down until tomorrow…
There is a library of mounting holes. Scroll to M in footprints.
Yeah; Unfortunately I needed some weird sizes that were not in the original library. So I ended up modifying those footprints to make these ones.
Looking at the 3D viewer they seem to achieve what I was going for with the cutouts in the PCB.
Just for reference; mounting holes are as easy to modify as any other footprints.
If a/some modified mounting hole is/are required for one project, place one, modify and duplicate. If you wish to keep the modified one for future projects, modify and keep in a personal global library.
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That is exactly what I ended up doing! 
It was really convenient being able to create the footprint, then place it as needed. I was reverse engineering this PCB from the gerber files so I was trying my best to replicate the original polygon shape that was imported from that.
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Alright, I’ve connected all the ground pads with tracks according to the ratsnest. When I perform the fill though, I’m still being left with Isolated Copper Islands. There’s about 17 of them as I was able to clean a few random chunks of copper that were created by the fill with a no fill zone.
I believe I should be able to just place a VIA over top of these existing isolated islands, to connect them to the bottom layer which doesn’t show an island. However I’m still not seeing the DRC remove the warning about the copper island when a VIA is placed. I’m pretty confident I’m connecting the two ground plane layers, with this VIA.
I’ve uploaded the updated .kicad_pcb file here as well
StrumPCB_WithAccelerometer.kicad_pcb (1.6 MB)
You still have 4 errors which have to do with the solder jumpers.
There is a ratsnest line between the pads of the jumper.
This cannot be right. The two sides of an open jumper should be on distinct nets. Are you working without a schematic?
It also didn’t remove islands for me but I think you have to solve this jumper issue first.
I unfortunately am working without a schematic; The original PCB did not include any kind of schematic to reference which has made reverse engineering the gerber file into a modifiable form a bit challenging to say the least.
There was a documentation file regarding soldering however and I was able to find the following snippet which reference these pads. It seems to suggest they’re intentionally not connected:
If you are only using the smaller SK9822-EC20 LED package,
you need to bridge 4 small jumpers on the strum PCB. Doing
this will pass through GP2 and GP3 to the fret, bypassing the
strum LEDs.
In your position I think I would spend the time to also reverse engineer a Schematic . . . you know all the components (otherwise you cannot place the correct PCB footprints) you know how they are connected because you have the Gerbers. For the benefit of my sanity (and my pocket) I would make a schematic . . .
I don’t really think I need the schematic any more, the PCB is pretty much completed at this point. Aside from the isolated copper islands which I cannot seem to figure out how to resolve. The ground plane is something that I’ve manually created and added to this PCB as I’ve modified certain sections to include components that will be manually soldered to the board.
I’m really not sure why when I place a VIA to connect the top copper layer and bottom copper layers the two aren’t considered as “connected” by the DRC. This is really the only concern that I have for the PCB, I’m rather confident the PCB will otherwise be functional once it’s fabricated.
Whether the jumper is open or not, the two sides should have distinct nets. You’ll have to rename one side.
As for the isolated copper islands I get those too even though Remove Islands is Always. It may be a bug triggered by not having a project file. If somebody else can replicate the problem, it should be reported.
There was also some strangeness with the mounting holes I don’t understand.
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The normal way for KiCad to work is information created within the schematic is used to validate what is created in the PCB layout, by not having a schematic you are making life difficult for yourself and KiCad.
Have a read of this thread to understand some of the challenges that the development team have faced during the evolution of KiCad and why, in my opinion, you should try and make life easy for KiCad so you can get the best out of it.
Thanks for all your advice and suggestions so far. I’ve gone ahead and corrected that error was well by adjusting the name of the two nets like you suggested.
I thought it was strange that when Remove Islands was enabled, islands were in fact not being removed. I’ve managed to cleanup most of the isolated copper islands by creating a Rule Area that specifies not to fill those sections. This has corrected the majority of the isolated copper islands.
The last three isolated copper zones are pretty large and I figure they should be relatively easy to connect with a VIA; Though for whatever reason I just cannot get this to work the way I expect it to.
I’ve uploaded all the the kicad_pro and kicad_pcb files I have here.
Strum PCB Files.7z (264.2 KB)
Thank you, that looks like a rather detailed amount of information; I’ll give it a read through tomorrow. I don’t think it would be relatively difficult to create a schematic for the PCB, I just know it’s going to be time consuming. I also do not think the schematic should be necessary to connect the top and bottom copper layers in the PCB Editor. That would be a bit of a silly design choice in my personal opinion if that is indeed the case.
Regardless, a complete project is never a bad thing so I will consider reverse engineering a schematic as well.