No…I am just looking at all of the error/warning arrows (bright green in my image above.)
You’ll have to cope with the other denizens. They’re an eclectic bunch. 
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I don’t seem to get the same errors when I run my DRC. They’re a modified footprint for a “MountingHole” which I believe is considered a VIA, so that may be why.
One thing I just noticed; I guess that all of your footprints are locked. Probably not a root problem but just something to note for any of us trying to figure out your board.
I think I need to shut down until tomorrow…
There is a library of mounting holes. Scroll to M in footprints.
Yeah; Unfortunately I needed some weird sizes that were not in the original library. So I ended up modifying those footprints to make these ones.
Looking at the 3D viewer they seem to achieve what I was going for with the cutouts in the PCB.
Just for reference; mounting holes are as easy to modify as any other footprints.
If a/some modified mounting hole is/are required for one project, place one, modify and duplicate. If you wish to keep the modified one for future projects, modify and keep in a personal global library.
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That is exactly what I ended up doing! 
It was really convenient being able to create the footprint, then place it as needed. I was reverse engineering this PCB from the gerber files so I was trying my best to replicate the original polygon shape that was imported from that.
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Alright, I’ve connected all the ground pads with tracks according to the ratsnest. When I perform the fill though, I’m still being left with Isolated Copper Islands. There’s about 17 of them as I was able to clean a few random chunks of copper that were created by the fill with a no fill zone.
I believe I should be able to just place a VIA over top of these existing isolated islands, to connect them to the bottom layer which doesn’t show an island. However I’m still not seeing the DRC remove the warning about the copper island when a VIA is placed. I’m pretty confident I’m connecting the two ground plane layers, with this VIA.
I’ve uploaded the updated .kicad_pcb file here as well
StrumPCB_WithAccelerometer.kicad_pcb (1.6 MB)
You still have 4 errors which have to do with the solder jumpers.
There is a ratsnest line between the pads of the jumper.
This cannot be right. The two sides of an open jumper should be on distinct nets. Are you working without a schematic?
It also didn’t remove islands for me but I think you have to solve this jumper issue first.
I unfortunately am working without a schematic; The original PCB did not include any kind of schematic to reference which has made reverse engineering the gerber file into a modifiable form a bit challenging to say the least.
There was a documentation file regarding soldering however and I was able to find the following snippet which reference these pads. It seems to suggest they’re intentionally not connected:
If you are only using the smaller SK9822-EC20 LED package,
you need to bridge 4 small jumpers on the strum PCB. Doing
this will pass through GP2 and GP3 to the fret, bypassing the
strum LEDs.
In your position I think I would spend the time to also reverse engineer a Schematic . . . you know all the components (otherwise you cannot place the correct PCB footprints) you know how they are connected because you have the Gerbers. For the benefit of my sanity (and my pocket) I would make a schematic . . .
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I don’t really think I need the schematic any more, the PCB is pretty much completed at this point. Aside from the isolated copper islands which I cannot seem to figure out how to resolve. The ground plane is something that I’ve manually created and added to this PCB as I’ve modified certain sections to include components that will be manually soldered to the board.
I’m really not sure why when I place a VIA to connect the top copper layer and bottom copper layers the two aren’t considered as “connected” by the DRC. This is really the only concern that I have for the PCB, I’m rather confident the PCB will otherwise be functional once it’s fabricated.
Whether the jumper is open or not, the two sides should have distinct nets. You’ll have to rename one side.
As for the isolated copper islands I get those too even though Remove Islands is Always. It may be a bug triggered by not having a project file. If somebody else can replicate the problem, it should be reported.
There was also some strangeness with the mounting holes I don’t understand.
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The normal way for KiCad to work is information created within the schematic is used to validate what is created in the PCB layout, by not having a schematic you are making life difficult for yourself and KiCad.
Have a read of this thread to understand some of the challenges that the development team have faced during the evolution of KiCad and why, in my opinion, you should try and make life easy for KiCad so you can get the best out of it.
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Thanks for all your advice and suggestions so far. I’ve gone ahead and corrected that error was well by adjusting the name of the two nets like you suggested.
I thought it was strange that when Remove Islands was enabled, islands were in fact not being removed. I’ve managed to cleanup most of the isolated copper islands by creating a Rule Area that specifies not to fill those sections. This has corrected the majority of the isolated copper islands.
The last three isolated copper zones are pretty large and I figure they should be relatively easy to connect with a VIA; Though for whatever reason I just cannot get this to work the way I expect it to.
I’ve uploaded all the the kicad_pro and kicad_pcb files I have here.
Strum PCB Files.7z (263.9 KB)
Thank you, that looks like a rather detailed amount of information; I’ll give it a read through tomorrow. I don’t think it would be relatively difficult to create a schematic for the PCB, I just know it’s going to be time consuming. I also do not think the schematic should be necessary to connect the top and bottom copper layers in the PCB Editor. That would be a bit of a silly design choice in my personal opinion if that is indeed the case.
Regardless, a complete project is never a bad thing so I will consider reverse engineering a schematic as well.
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I do not agree with this sentence.
It can be the method used by beginner to check if zone will connect everything, but you write it as a rule to be used always which I disagree with. I left connecting GND to KiCad and I’m very happy with it.
Since 1997 till 2017 we used Protel 3. It was able to make connections while filling zones but had a vary big computation problem with it. Protel filled zones by making tracks around other pads and then filling whole area with horizontal and vertical tracks. I always left filling zones at the end as it worked much slower than in KiCad. Let us assume that filling typical PCB took about 10s. But if it happened you to left only one GND via not connected with tracks time was bigger - may be 20s. Time grew with some power of the number of connections left to be finished for filling zones.
At the beginning I didn’t know that and when I had PCB with about 20 GND vias that were not connected with tracks and run filling zones than after 30 minutes I decided to break its work.
The solution was as you write - to have DRC reporting no errors before adding zones to PCB.
So I was doing it this way but I felt compelled to stupidly connect all the GND vias I placed on the board.
With KiCad V4 I have also read that all stitching vias you should connect with tracks manually. But there were info that with V5 it will be working better. So even I made decision to go to KiCad when it was V4.0.6/V4.0.7 I decided to wait for V5 and spend this time on making my library structure and filling them with all basic elements to be used.
Since KiCad V5 you can just left connecting GND net pads to filling zone and with big pleasure I let it to KiCad. I just place GND via near GND pad and connect pad to this via and left rest to KiCad and for other pads I just do nothing.
The main problem here is failure to do a “proper” PCB design with a good GND plane. The GND plane should never have been cut up in so many little pieces.
Failure to make a good GND plane a very common (and one of the biggest) mistakes beginners make, and this topic is explained many times over. So do a bit of research.
For the rest, I don’t understand why this topic has 30 posts. I glanced though it and it looks like a lot of distractions.
No offense but you’ve not really provided any valuable or useful information here I can work from. I’ve done many hours researching across the forum, youtube and other tutorials. If I hadn’t I would not have posted in the forum to begin with. If you have some kind of reference material, please share it and I’ll take a look.
If you’re referring to the multiple locations there are GND Pads/VIAs this is necessary to allow for clean connections of the components to the PCB.
If you’re referring to the amount of tracks on both layers, which evidently is splitting the ground plane to begin with; This PCB is not my original design and was imported from a gerber file. I’ve made some minor modifications, the original PCB had numerous VIAs to stitch the ground plane together. Which is exactly what I expected to do with the 3 isolated copper islands that remain.
If you’re referring to the filled zone, which is now the ground plane; I only just made this zone and filled it. Initially, it was split with multiple islands due to the way some tracks are routed, however I cannot feasibly adjust these to ensure every single section on the filled zone/ground plane connects. This is why I expected to use VIAs to stitch the two layers together and complete their connections but as mentioned this does not seem to make KICADs DRC happy for whatever reason.
Additionally there are only three isolated copper islands left and in my opinion it’s a rather large ground plane, so I’m not sure what you’re referring to about it being “cut up in so many little pieces”. I believe placing a VIA between the two planes should connect the floating island to the other layer, which is already connected and not considered a floating island.
In regards to the amount of posts; People ask questions about the PCB, I assume to better understand the design to in-turn provide assistance to resolve the issue. I of course answered those questions to provide whatever insight I could.