Pre-emptively sorry for my terrible writing, grammar, wall of text, english, ocd and etc,
Right, sort of, except net naming is done automatically behind the scenes when the schematic is imported into pcbnew, when you first open/ create a pcb in the project, and when you update the pcb from the schematic. nets (and naming) is based on the footprints and global labels (so you can make custom nets/ label names in the schematic and have them be equivalent in the pcb with 1 click). so its not like you have to make a net with the same name, as much as making sure you assign whatever it is you want to the net you want, ie assigning the filled area to the net of the connector pin/ pad and setting it to the layer you want.
So here is an example of the filled zone properties (right click on the thingy) to set the layer you want it on and what net to be attached to (electronicly/ as per ERC) with the red arrows, with also showing adding a label to the schematic to change the net name on a pin with the yellow arrows.
And in the settings below is where you can set the specifics of the pad style for the connection from the zone to pins, and fill style and clearance (around none connected pins).
As opposed to vias that youll want to (and can) do the same through the pad properties, including the same settings for pad style etc, and also net association to electrically connect it. but that is more like only neccesary to use if you actually are fabbing blind/ buried vias, otherwise you wont set net association with vias, as any signal vias will avoid power planes as a result of the plane itself not being attached to the signals net and so avoiding it according to the clearance settings, and for any power or gnd vias, the power planes will get automatically connected to them and have any non-power regions avoid those vias.
As i understand it when you assign them to the same net or one to the other, they become part of the same net electricly (for ERC) and hpw they will appear is defined by DRC (hence the clearance dimensions that GyrosGeier meant by ‘pull back’ and the inclusion referenced by SembazuruCDE’s ‘thermal relief’ and shown in your own screenshots). you can see the list of nets in from the inspect menu up top, and youll noticethier behaviour in kicad if you select one and then all the pads connected to/ associated with that net will be highlighted.
but anyway you dont have to worry about nets for the most part as its automatic, tho if you want to, one thing you can do is use add global labels to electrical connections in eeschema, then when pcbnew is updated those nets will have that name (for easier/ custom navigation and viewing etc), also you can goto inspect menu> list nets, to see the name of nets currently incase your having trouble identifying the name of a net to assign, then its a case of editing the properties of the pad to either assign it to a specific net
so ultimately the only thing maybe ‘wrong’ about your first image is having the vias themselves at all (unless it was that that kikad used to link the nets of the pins to the layers in the first place, where they wernt linked before and if you remove the vias now they remain linked), so if you want power planes then assigning the relevant planes/ areas to the pins (like in SembazuruCDE first screenshot, and as opposed to assigning the pins to the areas), by selecting the pad and right clicking> properties, to assign it to a net (where if you were fabbing blind vias you could assign the sequential layers instead of ‘all copper’ default), and then in the clearance you have there where you can set the copper ‘pull back’/ relief clearance for exclusion area, and the type of pad connection (solid/ thermal relief etc where its likely that thermal relief was a default of those pins footprints in the library, hence not solid by default) for the case of it being pysically connected. so again it was only minorly wrong that you might have used vias to connect the pins to the layers you wanted instead of linking them with a net and then letting drc connect them, but then again you will probably want to use vias around your pcb for stitching and loop inductance reasons anyway so its not a problem, just this specific case has its own way of sorting out.
if your paranoid aswell as checking the render in transparency with solid copper shown, you can check also in layout by: on the ‘visables’ window to the right going to the ‘render’ tab and turning off footprints to see just the copper, so you know exactly whats going to be etched and if it makes sense for your connector.
last image shows plane updated after changing pad shape (also wild clearance)
hope this answers your qs, like you can overlap the areas if they connect only to pins on the net they are attached and avoid pins (and vias) that are not that net, and etc