Hi, thanks for your response. I am not sure what you mean by pulls back?
I am not using nets on this board as it stands…
Do you specifically see anything wrong with what I have done so far?
Sure you’re using nets: the pads in your schematic are labeled “+5V” and “GND”, these are the net names. The zones need to use the same net names, so they connect.
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Okay… So how do I name the zones. Also can you answer my other questions?
Also, those nets come the pads of the barrel jack, the rest of my circuit don’t use nets. Do I need to use nets to use vias?
Pcbnew does not update the zone boundaries automatically (which would be very slow). If you have drawn tracks on a layer, you have to press “b” to recalculate the zone boundaries to see your results properly.
To get an ever better view of what you are doing on the PCB you can start the 3D viewer [Alt + 3] and then turn off both the “board body” and the “Solder mask”
3D_viewer / Preferences / Display Options / Render / [ ] Show board body.
3D_viewer / Preferences / Display Options / Board / [ ] Show solder mask layers.
This will make most of your board transpararent (especially if you also disable:
3D_viewer / Preferences / Display Options / Render / [ ] Show filled areas in zones.
And with such a “transparent” board you can see all the via’s and tracks inside the board. It looks like:
Because of limits in manufacturing (cheap boards) all via’s go completely through the board. (The other kind of via’s are not yet within your grasp).
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When you draw a zone or edit it later, you can select the net. Here is an example where I have a zone assigned to the +5V net:
Did you start with a schematic in EESchema? If so, even if you didn’t name nets you are using them. Nets are how the schematic describes to the layout program which pins are connected to which other pins. The term net is short for “network of connections”. See the wikipedia entry for Netlist.
Any plated through hole (both THT pads and vias) will connect to any copper on any layer that is part of the same net. This includes zones and traces. You don’t need to draw traces and drop a via off your connector to get the pins connected to the proper zones. They are already automatically connected, see the thermal relief connections on your screenshots.
Vias are used to move to another layer while laying copper traces for a net. This can be to get past traces of a different net, to connect to a SMT pad on a different layer, or to follow layout guidelines if they exist. (It used to be a common guideline to have vertical traces on one layer and horizontal traces on another layer, especially on fully THT boards.) This includes non-named nets like, for example, the Net-(C2-Pad1) net in my screenshot, above.
Hi, yes I made a Schematic.
If there is a net for each connected component, then my Layer 1 will have lots of nets on it…so I suppose this particular technique is only useful for the GND and VCC layers in my board.
If I draw a trace with a net of “5V” and drop a via, will PCBnew automatically get the via to the right layer based upon the net (assuming that a layer “5V” exists? I will still however need to perform the trace and via placement though?
I also ask again — Does anything look wrong with what I have done so far in my original post? Or is all of this general advice building on my correct starting position?
How can I look at the properties of a via — to see what layer it connects to?
That’s a great tip - looking forward to giving this a go.
vias are on all layers by definition (they are simple plated through holes that can be connected on any layer)
If you want vias that are only between specific layers then you need to use blind or buried vias. But these will not come cheap in manufacturing. And it might not be the case that you can place them between any layer pair.
That’s very true. Basically you have to decide in advance which manufacturer you will use and know exactly what they can do. Many cheap manufacturers don’t do blind/buried vias at all. I’m not 100% sure, but if in KiCad you can choose the start and end layers for a via you are using blind/buried vias and will pay 5x or 10x price compared to through vias. Do it only if you have extreme size restrictions for the board.
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Hi Rene,
So to confirm, if I want a normal via (not buried / hidden), does that mean that I can’t have my Ground layer directly on top of the same shape as my 5V layer - as that would create a short?
That means that my Layer 2, Ground, would be the only plane on that area of the board…and likewise with the power, as per this:
KiCad is smart enough to automatically make a clearance around your vias for anything that does not have the correct net.
However you always need to refill the zones with shortcut B to see that result.
@Rene_Poschl – are you saying the diagram in my previous post is not correct? i.e I CAN have Layer 2 directly on top of Layer 3(overlapping in positional terms) and the Vias will still route correctly to the Layer 3 somehow without shorting through Layer 2?
Yes exactly. Simply try it out for yourself.
Or look at one of my 4 layer projects like this one: https://github.com/TERA-TU-Graz/BatteryManagement_2017/tree/master/HW/projects/fennek_2017_18/BMS/measurement_and_balancing/bms_board_V6-1__12s_fennek2017
Notice how there is a clearance around all of the vias.
And especially notice the Vmiddle via that has a clearance only on one of the layers
Ok – and this relies on having Nets associated with specific wires in the schematic, with the correct Label, and that way Kicad will automatically add the clearance to other layers?!
Wonderful!
It behaves exactly like THT pads with 2 layer designs. You can have THT pads inside zones with different nets and there’s no problem. With a 4 layer design you just add more layers.
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You do not need to manually assign nets. The schematic to pcb translation does this automatically.
But if you want to have easy to understand nets than yes you will need labels (easy to read nets are kind of what you want for copper zones)
Okay - so the net must be named according to the pin name, which is how Kicad’s ‘magic’ works.
The nets between signal pads are less important for me to name when dealing with VCC and Ground planes I assume, as I will be drawing traces by hand for these on one layer only.
Pre-emptively sorry for my terrible writing, grammar, wall of text, english, ocd and etc,
Right, sort of, except net naming is done automatically behind the scenes when the schematic is imported into pcbnew, when you first open/ create a pcb in the project, and when you update the pcb from the schematic. nets (and naming) is based on the footprints and global labels (so you can make custom nets/ label names in the schematic and have them be equivalent in the pcb with 1 click). so its not like you have to make a net with the same name, as much as making sure you assign whatever it is you want to the net you want, ie assigning the filled area to the net of the connector pin/ pad and setting it to the layer you want.
So here is an example of the filled zone properties (right click on the thingy) to set the layer you want it on and what net to be attached to (electronicly/ as per ERC) with the red arrows, with also showing adding a label to the schematic to change the net name on a pin with the yellow arrows.
And in the settings below is where you can set the specifics of the pad style for the connection from the zone to pins, and fill style and clearance (around none connected pins).
As opposed to vias that youll want to (and can) do the same through the pad properties, including the same settings for pad style etc, and also net association to electrically connect it. but that is more like only neccesary to use if you actually are fabbing blind/ buried vias, otherwise you wont set net association with vias, as any signal vias will avoid power planes as a result of the plane itself not being attached to the signals net and so avoiding it according to the clearance settings, and for any power or gnd vias, the power planes will get automatically connected to them and have any non-power regions avoid those vias.
As i understand it when you assign them to the same net or one to the other, they become part of the same net electricly (for ERC) and hpw they will appear is defined by DRC (hence the clearance dimensions that GyrosGeier meant by ‘pull back’ and the inclusion referenced by SembazuruCDE’s ‘thermal relief’ and shown in your own screenshots). you can see the list of nets in from the inspect menu up top, and youll noticethier behaviour in kicad if you select one and then all the pads connected to/ associated with that net will be highlighted.
but anyway you dont have to worry about nets for the most part as its automatic, tho if you want to, one thing you can do is use add global labels to electrical connections in eeschema, then when pcbnew is updated those nets will have that name (for easier/ custom navigation and viewing etc), also you can goto inspect menu> list nets, to see the name of nets currently incase your having trouble identifying the name of a net to assign, then its a case of editing the properties of the pad to either assign it to a specific net
so ultimately the only thing maybe ‘wrong’ about your first image is having the vias themselves at all (unless it was that that kikad used to link the nets of the pins to the layers in the first place, where they wernt linked before and if you remove the vias now they remain linked), so if you want power planes then assigning the relevant planes/ areas to the pins (like in SembazuruCDE first screenshot, and as opposed to assigning the pins to the areas), by selecting the pad and right clicking> properties, to assign it to a net (where if you were fabbing blind vias you could assign the sequential layers instead of ‘all copper’ default), and then in the clearance you have there where you can set the copper ‘pull back’/ relief clearance for exclusion area, and the type of pad connection (solid/ thermal relief etc where its likely that thermal relief was a default of those pins footprints in the library, hence not solid by default) for the case of it being pysically connected. so again it was only minorly wrong that you might have used vias to connect the pins to the layers you wanted instead of linking them with a net and then letting drc connect them, but then again you will probably want to use vias around your pcb for stitching and loop inductance reasons anyway so its not a problem, just this specific case has its own way of sorting out.
if your paranoid aswell as checking the render in transparency with solid copper shown, you can check also in layout by: on the ‘visables’ window to the right going to the ‘render’ tab and turning off footprints to see just the copper, so you know exactly whats going to be etched and if it makes sense for your connector.
last image shows plane updated after changing pad shape (also wild clearance)
hope this answers your qs, like you can overlap the areas if they connect only to pins on the net they are attached and avoid pins (and vias) that are not that net, and etc
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