Hello…
Does I do something really wrong or there is some insane thing in net naming. I usually use (local) net label in two situations. To name net between multiple symbols without placing any wire. Other situation is to place label on wire connecting multiple symbols. In that case seems that I can place different labels on same wire and that’s nonsense for me. There should be possibility to place label multiple time but with same value!. From previous software I use this have elegant solution. If I try to place net label on wire allready have net label the allready used name is used as default. (so you know that you click allready known net). But if you change that default the old label is updated with new net name.
Just discovered that I can even connect two global labels with wire without any warning.
I think in such subjects there are always two schools possible. Program knows better then you what you wont, or program allows you to do what you wont. I prefer the second school.
My example of using that approach. Once upon a time I had defined two GNDs and many elements connected to GND and other to AGND. When all elements were placed and connections routed (signals from GND region to AGND routed close to each other) I have added to schematic the connection between GND and AGND and made it just under lines going between them.
It is you, who knows what you wont. Program should not be against you. I would be at least unhappy if I had to change all AGND symbols through half of my schematic to GND to finalize that PCB.
At PCB it is the program task to not allow you to connect what is not connected at schematic, but when you draw schematic you are the master, I think.
I think you should get a warning when running ERC if you connect different labels with each other. (Tested in current nightly but i seem to remeber this also being the case in 5.1.7)
KiCads is build around the idea that you can do anything. It then offers tools to check your work that you can trigger when you think you are ready. Same with the pcb sync. The user is simply always in control when something happens. This means no annoying popups while you are in the middle of something at the cost of you needing to remember to trigger the check tools at the end.
Then, by right clicking on the error, you can “exclude” it from the warnings and ERC does not show it anymore, unless you enable the “[x] Exclusions” checkbox at the bottom of the dialog.
It was already known that ERC makes an error. What @eSlavko expected was that you get a popup or some other warning when you try to connect a label to one with a different name.
I seem to remember eagle worked that way. However eagle is a bit different with regards to that. In eagle you really set the netname. You don’t have abstract pointers (labels) that just happen to be used as part of the automatic net name generation.
I think this is why a dialog message would be unacceptable: you can have an intermediate state where you first add a new name and then delete the old. Also changing wires/nets would lead to such situations. But an infobar message would be OK because it’s not interruptive.
hm, I’m not a fan of message boxes interrupting the flow, and definitely not a fan of the infobar as it’s currently implemented. I’d propose thinking about ERC diffs - currently it’s rather hard to figure out what changes did when ERC messages are hidden in a bunch of previously discovered ERC violations while the work is in progress.
I think the easy solution can be simple. If we try to name the net and that allready have the name then just put that name in entry field for new name. So if it’s done by mistake clicking wrong net then in same moment you see that net is allready assigned and not few hours latter when DRC popup error.
This does not work with KiCad’s current workflow in which you type in the label name before you place the label somewhere.
Labels also often get connected by (block) moves.
For example, for a databus, I am used to placing a label with “D0” somewhere, then hold the [Ins] key to multiply that label and then use a block move (together with rotate and mirror) to get the labels to the right place.
I am quite happy with the current method of silently connecting nets with different labels and the ERC as a gentle reminder of possible errors.
@eSlavko
Don’t mix up ERC (Electrical Rules (inputs and outputs and such) in EEschema) and DRC ( Design rules such as clearances etc in Pcbnew) .
It would work when a new label is created by using the context menu of a wire -> Add label. It might be worth reporting as a feature request. The dialog could even show some information about possible conflicting names, so it would work as a pre-erc checker.
EDIT: I didn’t read eSlavko’s latest comment carefully enough.
