I Don't Understand a DRC Error Message

I am trying to add a MPM3610 5V Buck Converter to my pcb. I downloaded the footprint from the MPS website (linked to UltraLibrarian - MPM3610 | 21V Input, 1A Module Synchronous Step-down Converter with Integrated Inductor | MPS).

I keep getting the error “Front solder mask aperture bridges items with different nets” for pins 4,5,6, and 7,8,9. I am not sure what this error means, and how to fix it. I opened the footprint in the footprint editor and ran the footprint checker, and it came back with no errors.

Note: pins 4,5,6 are not connected to anything except a copper pour for thermal performance as per the datasheet.

Should I just ignore this error? I am not sure where else I can get a footprint for this part.

I am also getting a lot of “Clearance Violations” for this chip:


Do I ignore these errors?

It looks that polygon has no net, and ‘no net’ is different from pads 4,5,6 net.

The copper pour region was connected to the right signal on the board - pin 4 of the chip.

I edited the schematic to disconnect pins 4,5, and 6, and added “no connect symbols”. I removed the traces connecting these three pins, but kept the copper pour as per the datasheet. I still get the same errors for these pins - Clearance Violations and Front Solder Mask Aperture Bridges.

In KiCad a “polygon” (See DRC message window) is a graphical entity, and in general it should not be used in footprints on a copper layer. In KiCad V8 a netname can be assigned to a graphical entity, but not in earlier versions. I also do not know if the polygons in your footprint are on the other technical layers (solder mask and such).

I had a short look at the datasheet to get a better idea of how to solve it and saw:
image

So, I would replace the polygons with pads. Pads with different pad numbers may overlap in the footprint, as long as the netlist agrees that these pads are of the same net.

Some other notes:
I would use corner rounding for the pads. This has several advantages, and no disadvantages.

I would give each of the GND pins it’s own via on the PCB.

I have never used polygon at copper layer. There were some changes when V7, V8 were released so may be it is now allowed. I don’t know.

I assume you are talking about the polygon under the chip connecting pins 4,5,6. That polygon is part of the footprint I downloaded. I did not add it.

I did add the copper region on the outside of the chip on the left connecting pins 4,5,6. as per the datasheet. I also looked at the pcb layout from Adafruit for this same chip. I have used their 5V Buck Converter board, so I know it works. I am just copying that design on my board.

This is what is in the footprint editor for the part I downloaded from MPS:

I have attached the footprint file I downloaded from MPS.
ul_MPM3610GQV-P.zip (7.4 KB)

@paulvdh Did you mean replace the polygon in the footprint with a pad?

Assuming yes, I also had to delete the F.mask and F.paste layers for that F.Cu polygon, too. This did remove the error messages for pins 4,5,6 as shown.

The copper pour region on the left has the net U501-SW-Pad4, but will not “connect” to the pins 4,5,6 even though the net list is correct. If I make pads 4,5,6 and the big pad 4 Connection to Copper Zones override “Solid”, then the pcb shows the copper plane on those pads.
Screenshot from 2024-06-26 13-50-57

If I use “Thermal Relief”, which I think it should be, the copper pour does not show a connection to the pads.
Screenshot from 2024-06-26 13-52-10

Am I misunderstanding the pcb display, and should these pads be Thermal relief, since the only purpose of this extra copper is for thermal relief.

The other problem pads (7,8,9) are the 5V output pads. I connected them as shown (I haven’t replace footprint’s polygon yet). The vias connect to the inner layer power bus.


Should I extend the copper region to the pads and make their Connection to Copper Zones Solid, or Thermal Relief? Or, is it better practice to use traces as I have shown?

Yes, that is what I was talking about, and I already suspected it was part of the footprint itself.

Footprints from those big footprint sites are often not perfect. They are created from a big internal database (million or more footprints) and then exported for a bunch of different PCB design suites.

Learn to use the Footprint editor in KiCad, and then replace these polygons with real pads. (And also do the pad rounding thing for the other pads).

Every time and again I read about people who are hesitant to learn to use the footprint editor. Apparently they assume everything can be found on the 'net or something, but this is not true. I’ve designed very special footprint for custom homemade parts, and footprints from those big footprint sites often need some modification. Personally I find good footprint creation and modification tools more important then big libraries. With a good editor, you can make any footprint you want or need in a reasonable amount of time, while searching the net is a hit and miss and you never know in advance whether it works at all or what the quality is. I find KiCad’s footprint editor quite good (although a bit sparse maybe) and it is a part of the reason why I started using KiCad (8 or so years ago?) in the first place.

@paulvdh Why are rounded pads better than rectangular? Aesthetics, or something else?

You can do a bit of reading from this forum search:

https://forum.kicad.info/search?expanded=true&q=IPC-7351C%20rounded%20pads

And among the search results:

More reasons include: sharp corners lift from the dielectric more, act as tin whisker nodes and make high voltage breakdown easier

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