Perhaps there is another area where those two zones are a little closer and hence the 0.06mm in the Clearance Report
I’m not sure we have enough info here to figure this out, hopefully the OP has the tools to get to the bottom of this . . . or its a bug.
Thanks for pointing that out.
Yes, I’ve set the netclass ‘P’ clearance to 0.12 mm, but I’m actually trying to achieve more than 0.1 mm clearance between the copper pours. The issue is that no matter what value I set, the clearance between zones ends up being either 0.06 mm or 0.07 mm—never what I specified.
In some parts of the board, it shows 0.06 mm, in others 0.07 mm/.08mm, which makes it really confusing. So even though the netclass appears correctly configured, the actual clearance when zones are filled doesn’t match the setting. That’s the core issue I’m trying to understand and resolve.
Also, when I run the DRC, no clearance violation is reported, even though the spacing is clearly below the value I set. That’s what makes this even more difficult to debug
The issue isn’t limited to just those two zones — I’m specifically facing this problem across all copper pours. No matter which zones I look at, the clearance ends up being around 0.06 mm or 0.07 mm, even though I’ve set a higher value in the netclass
That’s nice of you to mention, but the rule that is used to define that 60um clearance is not shown in your screenshots.
You seem to be using a lot of custom rules, and even different rules with the same name. IMHO custom rules are great to do special things, but they can also become confusing. I tend to use the regular methods as much as possible and use custom rules only when there is no other option.
You’re absolutely right — the rule defining the 60 µm clearance isn’t shown in the screenshots, and I really appreciate you pointing that out. That’s exactly the issue I’m trying to understand.
I’ve set the netclass ‘P’ clearance to 0.12 mm because I want to maintain at least 0.1 mm clearance between copper pours. But no matter what I do, the clearance ends up being 0.06 mm, 0.07 mm, or sometimes 0.08 mm in different parts of the board — never the value I set.
This problem isn’t limited to just one or two zones — it’s happening across all copper pours, whether it’s power or ground. The netclasses seem correctly configured, but the actual clearance after filling doesn’t reflect those settings.
What’s even more confusing is that the DRC doesn’t report any violations, even though the spacing is clearly below the specified value.
I’m still trying to figure out what might be overriding the clearance settings — maybe it’s a hidden or unintended rule I missed. Any help or suggestions would be really appreciated. I truly need to get this resolved.
Thanks for the suggestion!
Yes, I’ve already tried setting the clearance directly in the copper zone properties as well as in the netclass settings (I set netclass ‘P’ to 0.12 mm because I want to maintain at least 0.1 mm clearance between copper pours). But no matter what I do, the actual clearance still ends up being 0.06 mm, 0.07 mm, or sometimes 0.08 mm in various parts of the board — never the value I intended.
This issue is not isolated — it’s happening across all copper pours, including both power and ground. The netclasses look correctly configured, and the zone settings also seem fine, yet after filling, the result doesn’t match what I’ve set.
What’s even more puzzling is that DRC doesn’t flag any clearance violations, even when the spacing is clearly under the specified limits.
No, that is not true. You’re running in circles because you are looking for the wrong dragon. KiCad does not suck the clearance of 60um out of it’s thumb (KiCad does not even have a thumb). As a logical deduction: Somewhere in your project, a clearance of 60um is defined, and apparently this overrules the settings you attempt to apply to the zones.
In the screenshot from your clearance report, there is a scrollbar on the right:
And it’s a short bar, so it looks like there are 6 to 8 more pages of text of rules that KiCad went though. One or more probably define that 60 clearance rule that overrules the others.
In the post where you wrote that, you had two screenshots. One was zones in VDD and 3V3. That shows that the constraint for netclass P is applied, 0.12 mm. But we can’t know if you have measured any clearances for those nets.
Then you show a test which resolves to 0.06 mm. The cause is of course that “condition not satisfied” for every rule.
You should probably show the whole custom rule set, it’s easy to get some rule wrong. Then you have to choose two items which we all can recognize and talk only about them; otherwise we will be confused by screenshots which aren’t related to each other.
The easiest way may be to share the whole project, if possible.
thanks for the detailed explanation. To help resolve this, I can share the full project. What’s the best way to do that here? Should I compress it as a .zip and attach it, or is there another preferred method?
KiCad already gives you the facility to compress the entire project to a ZIP file, upload the ZIP file here . . .
Several people have now wrote multiple times that the problem very likely is with the setup of your custom rules, and apparently you have not yet done anything with that advise.
So go to: PCB Editor / File / Board Setup / Design Rules / Custom Rules and then:
If the clearances are now as you would have expected, then you can be quite certain that it’s because of those rules you deleted. As a bit more fine grained approach, you can start by deleting / modifying only rules that specify a 60um clearance.
I’m unable to share the file as it exceeds the 4MB size limit
I already checked the custom rules when I had DRC issues before (due to a syntax error). I’ve reviewed them again, and they don’t seem to be the cause here
I did not ask if you had once reviewed the rules (nor to post many screenshot). And cutting / pasting the text would have been both easier for you and for us compared to those screenshots.
What is the result if you go though the 7 steps I posted earlier?
(You can make a backup before you do this, just as extra security you don’t loose all your rules.)
Delete MPU.kicad_sch-bak (and others -bak) and zip will be smaller.
Yes, I thought that too, but I wanted to encourage Ryan to dive a bit deeper into his project and solve it himself instead of just letting us do all the work.
To me it looks clear where the problem is. The explanation can be found if you combine the generic explanation of the rule syntax in PCB Editor | 9.0 | English | Documentation | KiCad, and insideCourtyard().
EDIT: or actually just insideCourtyard().
Yes, the insideCourtyard rules are the reason. Here’s your rule set modified, you can try re-filling zones with this:
(version 1)
(rule clearance_U12
#( constraint clearance (min 0.09mm))
( condition "A.insideCourtyard( 'U12')")
)
(rule clearance_J9
#( constraint clearance (min 0.2mm))
( condition "A.insideCourtyard( 'J9')")
)
(rule clearance_U5
#( constraint clearance (min 0.07mm))
( condition "A.insideCourtyard( 'U5')")
)
(rule "length matching MII"
(constraint length (min 30.75mm) (max 32mm))
(condition "A.NetClass == 'MII'")
)
(rule "length matching MIIT"
(constraint length (min 27.7694mm) (max 29.4mm))
(condition "A.NetClass == 'MIIT'")
)
(rule clearance_U4
#( constraint clearance (min 0.07mm))
( condition "A.insideCourtyard( 'U4')")
)
(rule "length matching DQS0"
(constraint length (min 37.3mm) (max 38.4mm))
(condition "A.NetClass == 'DQS0'")
)
(rule "skew matching DQS0DP"
(constraint length (min 37.34mm) (max 38.4mm))
(condition "A.NetClass == 'DQS0DP'")
)
(rule "length matching DQS1"
(constraint length (min 36.0844mm) (max 37.1mm))
(condition "A.NetClass == 'DQS1'")
)
(rule "skew matching DQS1DP"
(constraint length (min 34.084mm) (max 37.1mm))
(condition "A.NetClass == 'DQS1DP'")
)
(rule "length matching DDRCON"
(constraint length (min 43.9mm) (max 45mm))
(condition "A.NetClass == 'DDRCON'")
)
(rule "Clearance DDR3 fan out"
(constraint clearance (min 0.07mm))
(condition "A.Type == 'Track' && B.Type == 'Track' && A.Net != B.Net && A.intersectsArea('DDR3') && B.intersectsArea('DDR3')")
)
(rule "length matching AC"
(constraint length (min 55.5448mm) (max 57.5608mm))
(condition "A.NetClass == 'AC'")
)
(rule "Clearance for phy "
#(constraint clearance (min 0.07mm))
(condition "A.Type == 'Track' && B.Type == 'Track' && A.Net != B.Net && A.intersectsArea('phy') && B.intersectsArea('phy')")
)
(rule "length matching SDIOSD"
(constraint length (min 79.421mm) (max 81.9604mm))
(condition "A.NetClass == 'SDIOSD'")
)
(rule clearance_U6
#( constraint clearance (min 0.09mm))
( condition "A.insideCourtyard('U6')")
)
(rule WIFIRF_CLEAR
(constraint clearance (min 0.2mm))
(condition "A.NetClass == 'WIFIRF' && B.Type == 'Zone'")
)
(rule DPMDI_CLEAR
(constraint clearance (min 0.375mm))
(condition "A.NetClass == 'DPMDI' && B.Type == 'Zone'")
)
(rule "length matching DDRCLK"
(constraint length (min 43.9mm) (max 45mm))
(condition "A.NetClass == 'DDRCLK'")
)
(rule "length matching SDIOWIFI"
(constraint length (min 83.1113mm) (max 86mm))
(condition "A.NetClass == 'SDIOWIFI'")
)
(rule clearance_J10
#( constraint clearance (min 0.09mm))
( condition "A.insideCourtyard( 'J10')")
)
(rule clearance_MOSFET3
#( constraint clearance (min 0.09mm))
( condition "A.insideCourtyard( 'MOSFET3')")
)
(rule clearance_J7
#( constraint clearance (min 0.09mm))
( condition "A.insideCourtyard( 'J7')")
)
(rule clearance_IC1
#( constraint clearance (min 0.09mm))
( condition "A.insideCourtyard( 'IC1')")
)
(rule clearance_U16
#( constraint clearance (min 0.09mm))
( condition "A.insideCourtyard( 'U16')")
)
(rule clearance_U1
#( constraint clearance (min 0.09mm))
( condition "A.intersectsCourtyard( 'U1')")
)
(rule clearance_U5
#( constraint clearance (min 0.07mm))
( condition "A.insideCourtyard( 'U5')")
)
(rule clearance_CR2
#( constraint clearance (min 0.06mm))
( condition "A.insideCourtyard( 'CR2')")
)
(rule signal_CLEAR
(constraint clearance (min 0.2mm))
(condition "A.NetClass == 'WIFIRF' && B.Type == 'Zone'")
)
(rule signal_CLEAR
(constraint clearance (min 0.2mm))
(condition "A.NetClass == 'RF' && B.Type == 'Zone'")
)
(rule signal_CLEAR
(constraint clearance (min 0.375mm))
(condition "A.NetClass == 'DPMDI' && B.Type == 'Zone'")
)
(rule signal_CLEAR
(constraint clearance (min 0.2mm))
(condition "A.NetClass == 'LR' && B.Type == 'Zone'")
)
Note also that you have “constraint clearance (min 0.06mm)” while the minimum clearance in the Constraints setup is 0.07. The Constraints has absolute minimum values which must not be violated (minimum manufacturer accepted values). However, I don’t understand why the algorithms don’t obey the minimum clearance Constraint and why DRC check doesn’t catch it as an error. For example the front GND zone around U12 fills to 0.06 mm against tracks.