Hierarchy - Bus NOT connecting

Cannot get a BUS to connect to another sub-sheet.
Made a simple Project, Hierarchy with two sub-sheets.

The First sub-sheet, called Processor has just Microchip PIC with two ports connected to a BUS.
Used BUS entry and named pins like the PIC (RA0 … RA7 and RB0 … RB7). I placed a Hierarchy Label on the BUS named PIC_BUS. Placed a Hierarchy Pin on the SUB sheet in the ROOT schematic with the same name using Auto Pin Placement Tool.

The Second sub-sheet, called I_O has two 1x8 pin connectors. Again on this sub-sheet schematic, I used BUS entries from a BUS wire to pins of connectors named the same RA0 … RA7 and RB0 … RB7. Again Placed a Hierarchy Label on the BUS named PIC_BUS. Again used Placement Tool to place Hierarchy Pin on the SUB sheet in the ROOT schematic.

I then connected these Hierarchy Pins with a BUS wire between the two sub-sheets connecting to the Hierarchy Pins.

When I run DRC I get unconnected pins, all the PORTS of the PIC and two 1x8 Connectors. Tried using a wire instead of BUS wire to connect the Hierarchy Pins, same unconnected errors.

Am I doing something wrong? I can make a simple RC circuit and connect it between the two sub-sheets just fine using the same methods as the BUS.

Thanks in advance,
OtG

Have you used hierarchical labels before?

Can you post your (whole or simplified) project here?
Or at least a few screenshots.

Without that it’s just guess work what may be going on.

Yes, with just simple wires. One in my test circuit works OK.

EASY AVR.kicad_pcb (51 Bytes) KiCad5TestNew.pro (688 Bytes) HierarchicalTest.sch (2.1 KB) HierarchicalTest.sch-bak (2.1 KB) HierarchicalTest-cache.lib (4.0 KB) I_O.sch (3.3 KB) I_O.sch-bak (3.3 KB) Processor.sch (4.0 KB) Processor.sch-bak (4.0 KB)

Not sure if project uploaded correctly, but here are screen shots …

I’m having some trouble with your files.
I downloaded them and put them in a directory and opened KiCad5TestNew.pro with KiCad-nightly 5.99, and it complains that it can not find a "KiCad5TestNew.kicad_sch.

Can you just zip the whole directory and upload it as a single file?

[Edit]
23:07u I opened HierarcicalTest.sch with kicad V5.1.10 and can now browse through the hierarchy.

23:09u It’s getting clearer now. The screenshot below does not work (as you can see from the many ERC error arrows)

image

The Blue bus wires in KiCad are mostly eye candy and KiCad relies on wire labels to make the actual connections, regardless if you’ve drawn a blue bus or not.

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I don’t know where those files came from. The Project was called “HierarchicalTest”. I’ll try and zip it.
OtGHierarchicalTest.zip (7.9 KB)

That is what I was starting to think. How should you do BUSes then?
OtG

There is a very limited support for getting numbered bus members through a hierarchical label, but the syntax is quite finicky. You have to label both the bus and the hierarchical labels like so:

And then also do that in the hierarchical sub sheet:

The screenshots are from: https://github.com/search?q=rosco_m68k

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Ah! Only ONE Letter ALLOWED? AND you have to name the BUS on the Root?
OtG

I think you can use any name, but the name has to be the same for the whole bus.

It’s been quite a long time I did this myself though and I’ve forgotten the details.

What is the BUS label on the Root? A Hierarchy Label?
OtG


Using Hierarchy Label I get these errors …
OtG

It’s hard to see from your screenshot, but the P[0.15] looks a bit yellowish. I think it’s a Hierarchical label. (You also need two dots, but maybe one is just missing because of the way you made your screenshot.

Hierarchical labels are only used to connect to other sheets.
If you look at my first screenshot you will see the text near the bus is black. It is a regular label to name the bus itself.

Yes I did see it was Black and I was using hierarchy label. By “regular label” do you mean Global Label? They have bracket around them. And it’s not a “Net Label”. So I’m confused as to what kind of Label I should use on the root schematic. I’ll check my dots … :wink:
Thanks for the help BTW …
OtG

All of the Labels and Pins have two dots.

The bus is just labeled with a regular “net label”.
If you still have doubts, then clone the rosco_m68k project from github and have a look at how they did it.

I tried with Net Label, still get unconnected errors … updated project folder attached.
OtGHierarchicalTest.zip (7.9 KB)

Look at my second screenshot.
You also have label all the wires where they enter the bus.

Ah, the project at work had all the pins labeled. I made all labels Pxx and it now passes DRC.
Going to be issue cause my real project (at work) has mix signals in the BUS. Hope this gets addressed new revision.
Thanks :wink:
OtG

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