Ground "errors"?

Schematic
#1

I’m new to this system, and have completed my first schematic.
I’ve corrected all the errors flagged by the ERC, but three remain.
These all relate to “Net 12” which the netlist shows as a net of grounds, and looks OK.
The three errors all complain that the pins are connected together.
In particular, I have made up a symbol for the NodeMCU, which has five appearances of “GND” - all designated as “Power Input.” Three are no problem; two show up as the errors.
Both the part and the Pin Table show all GND pins the same.

(Since the netlist seems OK, I intend to proceed to making a PCB, but I would like to know what is flagging the errors.)

Any ideas as to what the problem is?

#2

Without knowing the exact error message we can really only guess. A common problem seems to be not understanding how the supply check works so you might want to read this: ErrType(3): Pin connected to some others pins but no pin to drive it

Also keep in mind that any error is only listed once per net so if your power inputs are connected together then the error is only given once.

#3

Thanks for your great reference.
Unfortunately, while it explained to me a lot of what is really “going on,” it did not solve my basic problem.
A little further looking revealed to me a part of the problem - but still not the solution!

The ERC error report is this:

ERC report (5/22/2020 10:32:45 PM, Encoding UTF8 )

***** Sheet /
ErrType(5): Conflict problem between pins. Severity: error
@(2.750 in, 5.900 in): Pin 3 (Power output) of component PS1 is connected to
@(6.500 in, 3.400 in): pin 8 (Power output) of component N1 (net 12).
ErrType(5): Conflict problem between pins. Severity: error
@(6.500 in, 3.400 in): Pin 8 (Power output) of component N1 is connected to
@(6.500 in, 3.600 in): pin 10 (Power output) of component N1 (net 12).
ErrType(5): Conflict problem between pins. Severity: error
@(6.500 in, 3.600 in): Pin 10 (Power output) of component N1 is connected to
@(7.500 in, 4.000 in): pin 17 (Power output) of component N1 (net 12).

** ERC messages: 3 Errors 3 Warnings 0

I can understand having a problem with two “outputs” connected together.
However, when I made up the component “N1” I specified that pins 8, 10, 17 and 24 were all to be of type “Power Input.” All these are connected to ground. I checked with the “pin table” and all are still called “power input.”
The netlist says (for net 12) that pins 8, 10, 14, 17, 24 are all a part of net 12. All show up on the “pin table” as “power input,” and all seem to be identical. The only ones that the ERC complains about are 8, 10 and 17. (Incidentally, there is a part on the net 12 that IS a power output. Adding a “Power Flag” creates an additional error.)
I still have no answer, but now I see that while the pin table shows the five pins 8, 10, 14, 17, 24) all to be “power input,” somehow the ERC seems to think that 8, 10, and 17 are actually outputs.
I can’t think of what I may be doing wrong - but I’d like to know!
Any further ideas??

#4

Have never got such errors (I couldn’t got as I just don’t run ERC ever :slight_smile: ) but I suppose, now you will be asked to:

  1. give the exact version of KiCad you are using.
  2. if you can - zip the project and put here.

I believe someone will look inside and find the source of problem.

#5

There is a contradiction here! If ERC says a pin is power out then the pin is very likely to be power out. Is it possible you look at the wrong symbol when analysing it with the library editor? (Possible reasons could be: you have similar symbols in the lib and got confused, possibly even the same symbol name in different libs. You changed the symbol after you placed it and made a mistake in the rescue dialog or did not yet run rescue.)

PS: I assume you are on KiCad stable. If you are on nightly then it is slightly different but to be honest if pin types are strange to you then nightly might not be the best idea either.

#6

Thanks again, Rene.
My version is 5.1.6, released very recently.
I just tried a few things, unsuccessfully, but I think I’ll just give up on this topic - at least for now.
Although ERC finds errors, these seem to have to do with the pin descriptions - which I thought were OK, but as you point out MAY have differing versions which I simply have not caught. I did do some “fooling around” in the course of making up my part, and it is possible that there is an incorrect version of the pin description somewhere that is causing the ERC problem.

Since the netlist seems OK, I’ll proceed with making up the board.
Incidentally, the part I made up was a NodeMCU, which I couldn’t find in the library list of standard parts. Is there a chance that someone has made it up already, and included it in a library that I’ve not found? If so, it would simplify things for me, as I wouldn’t have to create a footprint.

Again, thanks for all the help!
- Matt

#7

Creating a footprint is much simpler task then designing the PCB.

2 Likes
#8

Will never understand why so often the engineers designing PCBs are so scared to create own footprints.

1 Like
#9

Indeed.
Before I decided on upgrading from my old EDA program to KiCad I evaluated some 8 different programs. One of the important criterias was the creation of custom footprints. KiCad was Pretty good in this regard. Back then it had some serious bugs in Library management itself, but those have been resolved years ago and it works with a few mouse clicks and typing a library name.

#10

I would assume these two tutorials might help:

#11

Regarding footprints.

  1. The last time I was involved with PCB design was about 30 years ago. Then I had someone working for me do it, and it seemed to be quite a chore for him.
  2. I doubt that I will ever have to design a PCB again, so it didn’t seem worthwhile to learn a new system.
  3. HOWEVER - using KiCAD it does seem quite easy, if not actually intuitive.

(My original problem, the ERC complaining that two of the five ground pins were determined to be outputs, when I had clearly made all five the same, and all were inputs, has still not been solved - but it is now moot, and I have moved on.)

#12

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