Errors & warnings in DRC check


I have a problem with errors and warning when I check the DRC rules.
I get many errors (209 to be accurate), and most of them seem to be
“ErrorL Front solder mask aperture bridges items with different nets”, whatever it means.
When looking at where exactly the problem arises, I get this:

So I suspect there is something with the thin line and the purple background of this line.
The thin line: does not correspond to any of my settings, at least not those in the board setup.
It is shown only if is selected.
I found out that the purple area around the pins is the layer F.mask.
So I suppose that Kicad is not happy that the purple area is larger than this thin line.
Can anyone tell me what is this thin line, and also how to adjust the width of the F.mask layer?
I tried to change a few things in the solder mask settings, but as the panel says that 0 is suggested,
I’m not sure I have to mess with that.

By the way, if I could also know why pin 1 shows this problem and also 19 and 20, but not pin 2,
it might help to understand what’s wrong.

Thanks for any hint.

You have huge mask clearance in the footprint or the pads or in Board Setup → Board Stackup → Solder Mask/Paste. First, read How does solder mask layer work?. It’s a bit outdated, I should update it for v7.

It is Clearance. To check it - change Clearance of Default net class (in Board Setup - Design Rules - Net Classes). But clearance can be also set at footprint layer or individual pads so changing it for Default net class doesn’t have to affect your lines.

I suppose that you have ‘Solder mask minimum web width’ (in Board Setup - Board Stackup - Solder Mask/Paste bigger than what left between your purple areas and they will be connected together so there will be one opening for pads having different nets and it is what Error message tries to tell you. I don’t know why Mask/Paste is under Board Stackup…
To check it - generate gerbers and see them.


Thanks for your replies.

It is Clearance. To check it - change Clearance of Default net class (in Board Setup - Design Rules - Net Classes)

I found the clearance and changed it successfully. But anyway 0.1mm seems to be fine, so I set it back, but at least I know how to change it.

Now this brings another question: why doesn’t the copper filling come right on the clearance line?

Screenshot from 2023-04-19 17-16-59

Where do I change the copper filling?
I checked the board setup.

  • Apparently no such setting in board stackup, obviously not in Text&Graphics. Design rules?
    The distance between copper and one trace is 0.2mm according to the grid.
    I tried to change anything in coppper but as you can see above, there is no setting of 0.2mm,
    so I haven’t found anything there.
    Obviously not in Holes, uVias and silkscreen.
    Pre-defined sizes is only for vias and traces. Custom rules is empty and violation severity is not relevant.
    And the clearance in net classes changes only the thin line, not the copper border location…
    Can the copper clearance be setup? If yes, where?

You have huge mask clearance in the footprint or the pads or in Board Setup → Board Stackup → Solder Mask/Paste.

I found the setup, thanks!

Where do I change the copper filling?

Thats a parameter in every zone properties dialog - clearance value. This can (and must) be set for every zone individually:

  • doubleclick zone-border → zone properties dialog → clearance value
  • or: select the zone (one LMB-click) → open properties panel on the left of kicad board editor → there is also a line with the clearance value
  • if you want to change the clearance value for multiple zones at the same time:
    • display properties panel at the left of board editor
    • display search panel at the bottom of board editor
    • in the search-panel–>zones-pane: you could Shift-select multiple zones
    • now the properties panel at left shows the parameters for these selected zones - so you can change clearance value (or other settings) for these zones with one action
    • this workflow can be used as “poor mans zone-manager”
  • attention for clearance to the board-edge, to holes and cutouts: this value is not the clearance value from the zone properties. For this the global board edge clearance from the board constraint setup is used (was changed in v7)


That was it, it works! Thanks!

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