I wouldn’t advocate hiding pins on an FPGA. Nice job switching the tracks though. FPGA has a multipin square box symbol with a multipad footprint - number all the pins sequentially and do the same for the pads on the footprint. Nice job giving an example that doesn’t contain a problem in the first place! I couldn’t help but notice that you avoided my example altogether.
Yes, using hidden pins and stacking them is far from best design practices. However it is not going to get resolved by yelling that it is not acceptable. In current software functionality sometimes that is the only reasonable thing to do. The best solution would be having an ability to assign multiple pin numbers to a single graphical pin to show internal connections.
That’s what we are talking about here - special cases when there is no other “pretty” way of doing it. Nobody even mentioned multi-pin chips here until your introduced it. Your concern for techs is admirable. Ok, so if I understood you correctly you are advocating placing multiple visible pins for the FET?
Is it going to help your imaginary tech? What are you going to do when there are four pins assigned to each side? What about five? Now imagine that you have to connect all those bundles of pins with wires on the schematic level. You going to end up with a giant ratsnest in your quest for schematic readability. No matter how you arrange the pins you are going to end up with a symbol that is not a standard symbol for a FET.
This case is nether rare nor imaginary. I have to deal with parts like that all the time. And it is not limited just to transistor parts.
That’s brilliant! Let’s replace all the symbols in the schematic library with multi-pin squares! It will do wonders to schematic readability and our hypothetical tech will be happy! It will significantly simplify symbol library too. Just find a square with a matching number of pins and you are done. None of those pesky transistors or resistors or diodes. Just squares. It will revolutionize electronics industry!
Even I didn’t realize we were limited to discussing only FETs, I thought it was about hidden pins in general.
I wouldn’t use that approach even if it were available.
Was I not clear enough in my previous post? One pin per pad.
I also stated that this was my opinion, you are of course free to have a different one, but so far your argument in support of your opinion is a bit silly.
No, but I admire your effort .
This is from one of my schematics:
Why do you keep referring to the human reader as “imaginary” or “hypothetical”? If no human was ever going to read the schematic then why do we even bother with pin names?
What is not “standard” about a five pin FET in PowerPAK packages?
Wow. So sorry. I didn’t realize it was you …I mean EVEN YOU! I take it all back
Without nitpicking the rest of your nuggets of wisdom, I’ll just say this (which pretty much amounts to nitpicking your nuggets of wisdom):
It wasn’t about hidden pins in general, it was about hidden pins where they can be used justifiably
You are free to use any approach you choose. Nobody can force common sense on you
You were crystal clear sir, one pin one pad. So sorry I described it as multiple visible pins…although I wasn’t even talking to you at the time. Regardless… Won’t happen again!
Thank you for allowing me my own opinion. I’ll try not to let you down by it being silly
It is a beautiful rendition of something with many legs. You are quite an artist yourself! Likewise, superb effort! This might be silly, and I apologize in advance, but it is not a symbol for a FET transistor. I think if it was a choice between the two, I would rather go with AndyP’s box schematic. Otherwise you would have those muli-legged bugs crawling all over the place! That’s not to mention that you would have to create each bug for each implementation of the part.
The tech was imaginary because we imagined it. This might come as a shock to you, but he really doesn’t exist.
Five pin FET’s are may be “standard” in PowerPAK package (that’s because PowerPAK packages have five pins…just making sure you knew), what is not standard is a five pin schematic symbol for a FET.
Hurry up and give us a couple more pearls of wisdom before Joan_de_Sparky comes and chops this discussion into pieces
