Hello:
It has been 16 hrs that I am struggling to design castallated edge vias- without any success- even though we have PCBs delivered with them using 5th & 6 releases…cannot go back. Seems our design approach was not general, somehow old design went through our supplier PCBWAY.
Anybody has a well-designed process for such PCB edges?
Any help will be highly appreciated.
r
I use a mix of THT and VIA’s. I created Footprints for them that contain SMD Pad’s.
Simple to do and depending on what/how you do it, the details with respect to who makes the PCB may dictate the approach.
It’s as much about learning to use Kicad as it is about design stuff… Best to confirm what your PCB source wants…
Does this help? What are the problems exactly?
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