DRC for ref des over a TH pad

[DiBosco]

Am just starting to use v7 and am delighted to find that errors are now flagged when a ref des is overlapping an SM pad, but it’s not flagging errors when the ref des is over a TH pad.

Is this me not using DRC correctly or is it not implemented.

If it is implemented how I do I get it to flag a ref des over a TH pad please?

Thanks.

Edit: I’m not sure I’m right about the DRC for ref des bring on a pad, I think it might be flagging an error because it’s clashing with the outline of the part which is bound to happen on smaller SM parts like 0603s

[baldengineer]

Share the error and a picture of where it is occuring.

[paulvdh]

DRC is not complaining about the pads (for me), but about “Silkscreen clipped by solder mask”, and for that it does not matter whether it’s an SMT or an THT pad.

[DiBosco]

I don’t get a silkscreen clipped by solder mask at all. Ever. For example:

However, if I put the ref des across the silkscreen outline like this:

Then I get a Silkscreen Overlap warning/error.

It’s the same for TH and SM actually, it’s just that I was thinking it was detecting it on the pads on SM because the part is so small with things like 0603; if the ref des clips the silkscreen it’s almost definitely going to clip the pad too.

[baldengineer]

Again, can you please post the actual DRC message you are seeing.

@DiBosco

I don’t get a silkscreen clipped by solder mask at all.
…
if I put the ref des across the silkscreen outline like this:

But those are two completely different DRC checks.

Silkscreen clipped by solder mask tells you that no solder mask is available for silk to print

While Silkscreen overlap tells you that two silkscreen elements are overlapping (and will be combined as one).

In File -> Board Setup -> Design Rules -> Violation Severity -> Readability what are your current settings?

For example, here is mine:

[DiBosco]

These are my settings,.

The only error I can get is this:

For a position like this:

I can put that C516 ref des all over the pad itself and as long as it crosses no silkcreen, no error is flagged.

[baldengineer]

Are errors enabled/selected in the DRC window?

[DiBosco]

Do you mean here?

[paulvdh]

Do your pads (SMT and THT) actually have a cutout in the solder mask? (All default KiCad Libraries do) What is the source of your libraries?

If you still can’t figure it out, then make a small test project. Maybe a few resistors or IC’s (SMT and/or THT) and a few connections. Then zip it up and post it here and we’ll have a look at it.

[DiBosco]

@paulvdh

Do your pads (SMT and THT) actually have a cutout in the solder mask? (All default KiCad Libraries do) What is the source of your libraries?

What do you mean by a cutout in the solder mask please?

I don’t use any default libraries, they are all self-created (other than the 3D models which I get from manufacturers’ web sites.)

[paulvdh]

A “Pad” is more then a feature on a copper layer. A lot of layers in KiCad have specific meanings (Look up the manual for specific details) and defining things such as soldermask and solder paste are parts that should be defined in each pad. If you define a pad in the footprint editor, you must enable these layers.

(For SMT pads you want F.Paste and F.Mask, for a THT pad you do not want F.Paste).

If you do not enable the soldermask layer (F.Mask) then your pads will get covered with solder mask. Soldermask is a “negative” layer in which the solder mask will only be removed if you draw features on it. By default it’s the same as the pad size (but you can modify this by some margin). It is also possible to do this in some other shape. In that case you disable that layer for the pad itself, and then draw an Aperture Pad (without copper and also no pin number) in the shape you want.

[DiBosco]

Yeah, I’m well aware of all that, I’ve been laying out PCBs for thirty-five years!

It’s this phrase “cutout in the solder mask” I’m not aware of and how it impacts a ref des being spotted when it overlaps a pad.

Here’s my front mask and front silkscreen being shown (copper is off), but I still have no error being flagged here.

[paulvdh]

I would have thought you knew that too after 35 years.

[DiBosco]

You thought wrong!

So, go on then, what does it mean? And how would it help trap this error?

[eelik]

How does solder mask layer work?

What is soldermask and how does these layers work in KiCad? Solder mask is physical substance applied to the physical board. There are holes in this mask which expose copper pads. [image] In KiCad (and other EDA) the graphical layer which represents solder mask is negative. Where there is graphics in this layer, the physical solder mask isn’t applied and there will be a hole in the solder mask. There are two values for solder mask in Board Setup: clearance and minimum width. [image] IMPO…

[DiBosco]

@eelik All of this was stuff I was well aware of - other than the need for solder mask to copper clearance to make the errors appear. Don’t understand what that has to do with the silkscreen layer I must say, buy hey, now it works. Thanks!

[Jonathan_Haas]

@DiBosco

Don’t understand what that has to do with the silkscreen layer

The point is that when you have a THT pad without solder mask cutout, you essentially just made a custom via. As there is no bare copper and everything will be covered by solder mask (the green stuff) it is no problem to print your refdes on it and KiCad won’t create an error. The problem appears only if you print your text on bare copper (or, less important, bare PCB material).

[DiBosco]

@Jonathan_Haas

The point is that when you have a THT pad without solder mask cutout, you essentially just made a custom via. As there is no bare copper and everything will be covered by solder mask (the green stuff) it is no problem to print your refdes on it and KiCad won’t create an error. The problem appears only if you print your text on bare copper (or, less important, bare PCB material).

The very fact you have a solder mask aperture means you are exposing the copper to the silkscreen (otherwise you can’t solder to it, be it SM or TH), so I don’t really get that as an explanation.

I still don’t get what this “cutout” thing is. It’s a term I’ve never come across before.

I’m well aware of how pads work. For many years in an old CAD system I had a padstacks file and would use predefined padstacks in any new footprints. With these you’d always specify the paste, mask and copper apertures from yet another file. So, none of this is about understanding pads/stacks and how PCBs work, it’s about specific kicad terminology and methodology I guess. There’ll be a lightbulb moment at some point!

[eelik]

@DiBosco

other than the need for solder mask to copper clearance to make the errors appear.

The clearance shouldn’t affect this. It should work with zero and != zero clearance. If not, it may be a bug.

Can you provide an example project, just a minimal example, where the DRC warning/error is and is not triggered, depending on the clearance? Assuming, of course, that there’s a mask “cutout” (which isn’t an official KiCad word, it just means a hole in the mask substance) on the copper pads.