Designing high current traces with vias

That helps thanks still with there was a better user interface for that KiCad.
Why can’t Altium be like Autodesk and offer an entrepreneur licence version?

Ok guys one last question I have thousandths of vias in my board now and it needs to go for manufacturing is it a good idea or they don’t charge for vias?

This will depend on the vendor. I’ve seen >1000 for some 100mmX100mm boards at some of the cheap places in China.

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For most vendors, I think the parameter you need to watch is “hole density” - the average number of holes per unit area. Every via has a hole in it, even though it may be covered by soldermask or filled with solder. I can’t give you any typical values that trigger a surcharge, since my boards have never been close to the limit.


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Quick thing to note here. It appears that current enters and leaves the board on the same board edge. Due trace inductance and IIR effects, the transistors neared the current entry/exit points may well be doing a great deal more work than those as the opposite end of those high-current traces. If at all possible, current should enter on one board edge and leave on the other. This will balance the inductance and resistance across all transistors.