Decoupling caps for ICs

To help me get the hang of KiCad, I’ve been trying to rebuild the schematic for an old Apple serial expansion card from the early 1980’s - something I can actually use. :wink:

In any case, laying out the schematic and designing the symbols has been pretty straightforward - which is saying a lot as I’ve never used EDA before. But I’m running into a little issue in making sense of the decoupling caps.

The original schematic lays them out as a power net with +12V and +5V rails, and doesn’t bother with VCC / GND connections elsewhere, of course. But I need to call out specific caps for each IC VCC, which I can do easily enough using wires and labels, as opposed to the typical +5V / +12V power symbol.

But I suspect this is a common enough design case that there’s other more efficient ways to handle it. Also, since decoupling caps need to be located as close to the IC power in as possible, ensuring that in the PCB layout certainly matters…

Is there any good guidance on this? I’ve seen one other post on the same topic, but it didn’t really give me anything I could easily dig into for myself.

I am not sure if I understand correctly, but there are many conventions for how to draw your decoupling caps

#1 Draw them and wire them to the component, if the design calls for many decoupling caps or you have many components in a sheet it gets cluttered very fast:


#2 Draw them besides the component that needs them, this is my preferred way of doing it, because this way I know which cap has to go near each device, it can get cluttered, but you increase the spacing to help out.

#3 Put all decoupling together in a corner of the design an forget about them, this keeps your designs clean and clear (most textbooks use this approach, I learned about decoupling very late in my EE career :frowning: ) , most of the decoupling capacitors have the same values, as such, you just have to remember which component needs them.


Of course, this is all just my opinion YMMV

The problem is that as far as the eeschema is concerned GND is all one net and VCC is all one net. What I normally do is number the capacitors in parallel with the ICs so that I know where each has to be placed at layout time. I’m overconstraining of course because if they are all the same type and value, then it doesn’t matter which one goes with which IC. It’s just OCD.

Though VCC and GND can/are used as default, you can use Global Label’s with specific names to organize groups. And, you can tie them to one-another while keeping uniquely labeled.

Also, there are other VCC/GND’s that may preferred…

Example below… Clicking the ‘Highlight Net’ icon shows (in pink) what’s connected/same-track.


I prefer method #2, because when laying out a board the decoupling cap should be physically placed as close as possible to the IC whose power/ground you are decoupling. This method would help me remember, at least I think so.

So method #3 is how the original schematic was drawn, and I duplicated that. But, of course, I need to call out which cap is connected to which ICC’s VCC for the PCB layout. The only real issue, I suppose, is ensuring that the correct caps are positioned next to the IC’s during PCB layout, and making sure it’s annotated correctly.

In that case, I presume approach #2 will be more expedient…

I use method #2. When selecting the component inbox new, it is highlighted in the schematic - super easy to figure out where to place the cap

Many multi unit IC symbols have power blocks. I prefer to group these on one sheet, each with the associated decoupling

I don’t suppose you could link to a good example of that?

Interesting that this new script appeared that places components on the PCB so that their position mirrors the one in the schematic. If you followed method #1 or #2, this script would automatically place your decoupling caps near the associated IC.

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I reckon it’s a non-problem. If you just make sure you allocate the right number of decoupling capacitors when designing the circuit and to put them on the schematic using whichever placement and labelling strategy suits you, then if you have any left over after component placement on the PCB, you’re like a mechanic who finds nuts left over after reassembling machinery. :rofl:

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If you want to force a releation between one specific pin and one specific capacitor then you might need to use net-ties to achieve this (this introduces a net unique to the capacitor and IC pin)

However, you might want to ask yourself the question if you really care which of the equivalent capacitors is at which pin. This might depend on your personal design philosophy. KiCads support options for this are currently simply limited but will get better in the future. Especially the introduction of native net-ties will help a lot and possibly also the new improved constrained based DRC system.

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