Thanks a lot!
This does the trick.
(rule prim_sek
(constraint clearance (min 4.5mm))
(condition “A.NetClass == ‘Sek*’ && B.Pin_Type != ‘*no_connect’ && B.NetClass == ‘Default’ || B.NetClass == ‘P-400V’”))
Just for my understanding:
‘No net’ pads are not part of the rule, so why does the 4.5mm contraint trigger at ‘no net’ pads?
Should I write a bug report for this?
Part of the problem is that all pads of a footprint who doesn’t have a dedicaded pin in the correspondending schematic symbol are automatically assigned to ‘Default’ net class.
Because net assignement in PCB is not supported this is only changeable if I edit the symbol and add the additional pins with the ‘not connected’ flag.
Bug report?
Furthermore I use a footprint converted from a Eagle lib.
All of the unconnected Pads in this footprint a assigned to ‘Default’ but without any netname.
Netname is blank an so ‘*no_connect’` can’t prevent rule violation.
Once again this is only changeable if I add correspondending pins in the schematic symbol with ‘not connected’ flag.
Bug report?