I think both those cases are covered by the functionality today, right? Those are the kind of net tie situations we already support. We just don’t support net ties with more than one set of shorting pins in a single symbol/footprint, as is needed for the current sense resistor.
yup, as you can see it works well and I have the bare card in front of me so yes this is support.
The only shortcomings with the present “net-ties” is they are a physical item and as such they have to be placed on the outer layers as they appear as a footprint and thus the associated area around such a “part”. Being able to bury them would be best.
Since the constraint is more on the footprint, some flexibility does exist as you could have a net-tie that is a narrow but tall trace connecting to a smaller pad IF there is a sense tap and thus a required change in constraint rules (track width). The only downside is all traces are obround so it would not terminate nicely and thus still take a reasonable board area to implement
Yup, we want to fix that limitation too. There are a few ways:
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We actually should eventually support “inner layer footprints” someday, they are important for some kinds of high-end PCB. It’s kind of related to the work being planned for advanced padstacks for pads and vias for V7, but I’m not sure how much will be done for V7.
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We also wanted to investigate being able to set a single pad as a net tie. There are a few different ways we could do this and it needs more investigation. But, if we can accomplish this in some way, it would let you get rid of the dedicated net tie footprints.
That`s good to hear.
Almost all instances of where net-ties are used are because some fork in a signal/trace is required: namespace isolation for ease of reading the cct and layout, some characteristic change on part of a signal/trace, means to stop the propagation of constraints (other constraints required at different parts of the physical layout).
At one point I was considering placing a load of net-ties down so I could have consistent clearance between digital traces (4H type thing), but I also needed to fan out from a BGA and also track onto a bank of SSOP’s The net-ties would have permitted fan-out and connection to the SSOP, leaving the bulk routing subject to the 4H separation. problem was the physical net-tie in v5.1.x and while the new constraints in v5.99 are great I don’t think they are flexible enough to do this
The way I would do this (in 5.99) is to give these digital traces a netclass, then have a rule that enforces the spacing on the netclass but then a different rule that relaxes the requirements for traces near the BGA (can draw a rule area around it and target it by name, for example)
I do not understand why net-ties have pads at all.
It is logical it’s implemented now in this way, as normally stuff is connected to pads of footprints.
Why not simply use a single track segment (Or copper zone) to act as a net-tie? This track segment would then be allowed to connect to 2 or more nets. This would also solve the problem of putting net-ties on inner layers.
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I am talking about the type of net tie that shows up on the schematic. The way KiCad’s internal systems work, it makes the most sense for this to be tied to footprints and pads. It is not possible now, and would not be easy to add, a way to let you draw a net tie on the schematic and have that forward to a particular track segment. Tracks and vias are more “temporary” objects that don’t have a direct connection to the schematic. Pads do have a direct connection to the schematic.
The improvements I describe should be flexible enough for most (all?) situations though. A net tie needs to have a particular location in general: just saying that a copper zone is allowed to connect to more than one net seems like a solution in search of a problem. I’ve never had a case personally, or heard of a case, where that was desirable, because it would mean losing control of where the two nets are shorted.
If you want to have a net tie away from a soldered component, that is fine: just use a net tie footprint that has a single very small pad with no soldermask. You can adjust the size of the pad to the size of the tracks you want to route to it, etc.
This would also solve the problem of putting net-ties on inner layers.
We need to support footprint pads on inner layers for various other reasons too, so being able to use them for net ties will “come along for free” in a sense.
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That description probably needs updating, by the way. It hasn’t really been kept up-to-date with some further discussions or the related work on pad stacks, etc
I am trying to keep this thread on topic as it is referenced by the issue tracker
Recently I had a design where it woud have been extraordinary useful to be able to place a net tie on an inner layer. That or use a via as the net tie out of a copper pour.
Could either of those (via as net tie, net tie on internal layer) possibly be supported in 6.0? I’ve been using the nightlies and the progress is incredible, but I still find this lacking.
In my design the power net was on multiple layers and I needed to get vds sensing across a mosfet. A net tie on top would be too large and cut out too much current carrying copper, so I needed the via connected directly to the plane by the fet. But the signal needed to run out on an internal plane. If I could place the net tie internally I could have done the isolation at the signal side of the via. But no internal parts.
I ended up deleting the net tie and using pour keepouts to isolate the signal. An extremely hacky solution.
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