That would explain this:
We really need to do first-class net ties…
It’s a hack before something more versatile exist. The part I don’t like is it is an actual copper part and thus can only go on TOP/BOTTOM.
So the 5.99 hack is a change that breaks backwards compatibility without solving any of the problems?
We did not intentionally change any net-tie behavior in 5.99 – if there are things broken, please open issues. We originally planned to have better net tie support for 6.0 but this got delayed to 7.0, so net ties should be just as hacky in 6.0 as they are in 5.x
Not so much, the report I linked looked like something about net-ties was removed but this broke old designs so it was re-introduced until something better comes along.
Some form of net alias is required where nets can have different names and then be part of different constraint groups.
Think about why net-ties are used? its because when it comes to layout something extra is needed to help influence the design - Two or more electrically connected nodes (sense resistor, reference point…) require different physical implementations
The plan for 7.0 is to allow footprints to specify that certain pads are allowed to be shorted to each other as net ties, but not others. This would solve this 4-wire current sense resistor case and also various others. Unfortunately this change is fairly complicated and there was not time to do it properly for 6.0
that sounds good and solves one part of the reason net-ties are used.
What about alias netnames?
Two cases I have dealt with recently
Sense resistor (see my screenshots above). I require the sense pins to be tracked as diff pairs and thus the _N and _P suffix
clock fanout to multiple ADC are driven from a buffer and thus net-ties are used to identify different ones
In the case 1, you can give the net names whatever names you want in the schematic. Your schematic symbol will still have 4 pins so you can give the sense nets your diff pair names as needed.
Edit to be clear: What I mean is that a current-sense resistor can be drawn as in davidsrb’s first screenshot at the top: a 4-pin device (not a two-pin device with separate net ties as in your reply). You will be able to say in the symbol editor that pins 1 and 2 should be shorted as a net-tie, and pins 3 and 4, but those two sets of pins cannot short to each other.
Can you say more about case 2 / post a picture?
Consider this
NOTE: it might be OTT to give each one a label but this is one example.
Another one is with Hierarchical blocks where without such a net-tie, whatever netname is connected to a hierarchical connection will propagate
This one was quite important because DCN had 2mm clearance (its 270V). Without the net-tie aspects of that constraint would have propagated to the sense circuit and well … try tracking a SOIC8 on 0.127mm pad spacing with a 2mm constraint - a violation at the tie was a small price to pay : NOTE this was done in v5.1.x and the newer constrain manager might make this easier, but there is still a need to label different parts of a net differently
I think both those cases are covered by the functionality today, right? Those are the kind of net tie situations we already support. We just don’t support net ties with more than one set of shorting pins in a single symbol/footprint, as is needed for the current sense resistor.
yup, as you can see it works well and I have the bare card in front of me so yes this is support.
The only shortcomings with the present “net-ties” is they are a physical item and as such they have to be placed on the outer layers as they appear as a footprint and thus the associated area around such a “part”. Being able to bury them would be best.
Since the constraint is more on the footprint, some flexibility does exist as you could have a net-tie that is a narrow but tall trace connecting to a smaller pad IF there is a sense tap and thus a required change in constraint rules (track width). The only downside is all traces are obround so it would not terminate nicely and thus still take a reasonable board area to implement
Yup, we want to fix that limitation too. There are a few ways:
We actually should eventually support “inner layer footprints” someday, they are important for some kinds of high-end PCB. It’s kind of related to the work being planned for advanced padstacks for pads and vias for V7, but I’m not sure how much will be done for V7.
We also wanted to investigate being able to set a single pad as a net tie. There are a few different ways we could do this and it needs more investigation. But, if we can accomplish this in some way, it would let you get rid of the dedicated net tie footprints.
That`s good to hear.
Almost all instances of where net-ties are used are because some fork in a signal/trace is required: namespace isolation for ease of reading the cct and layout, some characteristic change on part of a signal/trace, means to stop the propagation of constraints (other constraints required at different parts of the physical layout).
At one point I was considering placing a load of net-ties down so I could have consistent clearance between digital traces (4H type thing), but I also needed to fan out from a BGA and also track onto a bank of SSOP’s The net-ties would have permitted fan-out and connection to the SSOP, leaving the bulk routing subject to the 4H separation. problem was the physical net-tie in v5.1.x and while the new constraints in v5.99 are great I don’t think they are flexible enough to do this
The way I would do this (in 5.99) is to give these digital traces a netclass, then have a rule that enforces the spacing on the netclass but then a different rule that relaxes the requirements for traces near the BGA (can draw a rule area around it and target it by name, for example)
I do not understand why net-ties have pads at all.
It is logical it’s implemented now in this way, as normally stuff is connected to pads of footprints.
Why not simply use a single track segment (Or copper zone) to act as a net-tie? This track segment would then be allowed to connect to 2 or more nets. This would also solve the problem of putting net-ties on inner layers.
I am talking about the type of net tie that shows up on the schematic. The way KiCad’s internal systems work, it makes the most sense for this to be tied to footprints and pads. It is not possible now, and would not be easy to add, a way to let you draw a net tie on the schematic and have that forward to a particular track segment. Tracks and vias are more “temporary” objects that don’t have a direct connection to the schematic. Pads do have a direct connection to the schematic.
The improvements I describe should be flexible enough for most (all?) situations though. A net tie needs to have a particular location in general: just saying that a copper zone is allowed to connect to more than one net seems like a solution in search of a problem. I’ve never had a case personally, or heard of a case, where that was desirable, because it would mean losing control of where the two nets are shorted.
If you want to have a net tie away from a soldered component, that is fine: just use a net tie footprint that has a single very small pad with no soldermask. You can adjust the size of the pad to the size of the tracks you want to route to it, etc.
This would also solve the problem of putting net-ties on inner layers.
We need to support footprint pads on inner layers for various other reasons too, so being able to use them for net ties will “come along for free” in a sense.
That description probably needs updating, by the way. It hasn’t really been kept up-to-date with some further discussions or the related work on pad stacks, etc
I am trying to keep this thread on topic as it is referenced by the issue tracker
Recently I had a design where it woud have been extraordinary useful to be able to place a net tie on an inner layer. That or use a via as the net tie out of a copper pour.
Could either of those (via as net tie, net tie on internal layer) possibly be supported in 6.0? I’ve been using the nightlies and the progress is incredible, but I still find this lacking.
In my design the power net was on multiple layers and I needed to get vds sensing across a mosfet. A net tie on top would be too large and cut out too much current carrying copper, so I needed the via connected directly to the plane by the fet. But the signal needed to run out on an internal plane. If I could place the net tie internally I could have done the isolation at the signal side of the via. But no internal parts.
I ended up deleting the net tie and using pour keepouts to isolate the signal. An extremely hacky solution.
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